Techn. University, Diss., 2006--Darmstadt.

Chemnitz, Techn. Univ., Diplomarb., 2008.

Zugl.: Dresden, Techn. University, Diss., 2008.

Zugl.: Paderborn, Universiẗat, Diss., 2004.

Zugl.: Dresden, Techn. University, Diss., 2006.

Universiẗat, Diss., 2005--Jena.

Techn. University, Diss., 2007--Darmstadt.

4 mal im Jahr erscheinende Zeitschrift über aktuelle Themen der TU Chemnitz

This dissertation presents the results of research towards a new computer architectural approach for the construction of digital signal processors. The new approach is based on a transport triggered architecture (TTA) and allows for a dataflow processing mode. The proposed architecture has beed called TAD (Transport triggered Architecture with Dataflow-extension). The designed machine is able to execute limited dataflow-graphs using a single assembly instruction. The size of the dataflow-graph is limited by the number of available execution units and communication resources. To undertake the research a cycle-correct simulator of the proposed microarchitecture has been designed. Benchmark results of the new microarchitecture were obtained by executing typical DSP-programs on the simulator. The properties of the new architecture and the variants of its parameters are discussed in the text. i Performance data is given on a per-cycle basis. A demonstration machine for the TAD has been synthesized for a 0.35um CMOS-technology. Data for area and maximum clock frequency of the design have been extracted from the routed chip design. / Diese Arbeit stellt die Ergebnisse von Untersuchungen über eine neue Architekturvariante für digitale Signalverarbeitungsprozessoren mit transportgesteuerter Architektur (TTA) vor. Die dazu entworfene Maschine erlaubt es, endliche Datenflussgraphen auf einen einzelnen Maschinenbefehl abzubilden. Die maximale Größe der abbildbaren Datenflussgraphen ist dabei durch die Anzahl gleichzeitig verfügbarer Verarbeitungseinheiten und Kommunikationsresourcen beschränkt. Die Untersuchungen dazu wurden mit einem taktgenauen Mikroarchitektursimulator durchgeführt. Die Daten zur Verarbeitungsleistung der Maschine wurden durch das Ausführen von Lastprogrammen auf diesem Simulator gewonnen. Der Aufbau und die Eigenschaften der durch den Simulator realisierten Mikroarchitektur und einige von dieser Implementation abweichende Varianten werden erläutert. Da sich Angaben zur Anzahl der Verarbeitungszyklen nicht vergleichen lassen, ohne dass Informationen zur maximal erreichbaren Taktfrequenz der Implementation vorliegen, wurde die vorgeschlagene Mikroarchitektur als integrierter Schaltkreis synthetisiert, um Informationen zu Flächenbedarf und Laufzeit zu gewinnen. Aus den Entwurfsdaten für den integrierten Schaltkreis wurden die Verdrahtungs-Kapazitäten extrahiert und daraus die Information zur maximalen Taktfrequenz gewonnen.

It is a great research interest to integrate the Cell/B.E. processor into an AMD Opteron system. The result is a system benefiting from the advantages of both processors: the high computational power of the Cell/B.E. and the high I/O throughput of the Opteron. The task of this diploma thesis is to accomplish, that Cell-SPU code initially residing on the Opteron could be executed on the Cell under the GNU/Linux operating system. However, the SPUFS (Synergistic Processing Unit File System), provided from STI (Sony, Toshiba, IBM), does exactly the same thing on the Cell. The Cell is a combination of a PowerPC core and Synergistic Processing elements (SPE). The main work is to analyze the SPUFS and migrate it to the Opteron System. The result of the migration is a project called RSPUFS (Remote Synergistic Processing Unit File System), which provides nearly the same interface as SPUFS on the Cell side. The differences are caused by the TCP/IP link between Opteron and Cell, where no Remote Direct Memory Access (RDMA) is available. So it is not possible to write synchronously to the local store of the SPEs. The synchronization occurs implicitly before executing the Cell-SPU code. But not only semantics have changed: to access the XDR memory RSPUFS extends SPUFS with a special XDR interface, where the application can map the XDR into the local address space. The application must be aware of synchronization with an explicit call of the provided ''xdr\_sync'' routine. Another difference is, that RSPUFS does not support the gang principle of SPUFS, which is necessary to set the affinity between the SPEs. This thesis deals not only with the operating system part, but also with a library called ''libspe''. Libspe provides a wrapper around the SPUFS system calls. It is essential to port this library to the Opteron, because most of the Cell applications use it. Libspe is not only a wrapper, it saves a lot of work for the developer as well, like loading the Cell-SPU code or managing the context and system calls initiated by the SPE. Thus it has to be ported, too. The result of the work is, that an application can link against the modified libspe on the Opteron gaining direct access to the Synergistic Processor Elements.