Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 103-104).

Thesis (Ph. D.)--University of Washington, 2003. / Vita. Includes bibliographical references (leaves 96-101).

Thesis--Ph. D., University of Hong Kong, 1981.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 95-97). Also available in electronic version. Access restricted to campus users.

As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challenges to achieve power efficiency and cost targets for modern day high precision converter design. The main goal of this work is to study various approaches and then propose and validate the most suitable topology to achieve the desired performance and power efficiency specifications, up to 100 kHz bandwidth with 16-21 bits of resolution. This work will first study various analog-to-digital conversion architectures ranging from Nyquist converters such as flash, pipeline, to the delta sigma architecture. Advantages and limitations of each approach will be compared to develop the criteria for the optimal modulator architecture. Second, this work will study analog sub-circuit blocks such as opamp, comparator and reference voltage generator, to compare the advantages and limitations of various design approaches to develop the criteria for the optimal analog sub circuit design. Third, this work will study noise contributions from various sources such as thermal noise, flicker noise and coupling noise, to explore alternative power and die area efficient approaches to suppress the noise. Finally, a new topology will be proposed to meet all above criteria and adopt the new noise suppression concepts, and will be demonstrated to be the optimal approach. The main difference between this work from previous ones is that current work places emphasis on the integration of the modulator architecture design and analog sub-circuit block research efforts. A high performance stereo analog-to-digital modulator is designed based on the new approach and manufactured in silicon. The chip is measured in the lab and the measurement results reported in the dissertation. / text

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

There is ever-increasing demand in telecommunication system, data server and computer equipment for low voltage, high current power supply. LLC resonant converter is a good topology on primary side of the converter because it has soft switching and resonant conversion. However, the passive rectifier in the secondary side has high power dissipation. Synchronous rectifier is a popular method to reduce this rectification loss. Although there are many types of synchronous rectifier for PWM converter, most of them do not function well in LLC resonant converters. It is because the wave form of LLC resonant converter is different from PWM. The objective of this research is to reduce the power dissipation and physical size at the same time. In this thesis, a novel current driven synchronous rectifier with saturable current transformer and dynamic gate voltage control for LLC resonant Converter is presented. This novel circuit reduces the rectification loss and size of the current transformer in the synchronous rectifier. This synchronous rectifier has several outstanding characteristics compared with generic voltage driven and current driven synchronous rectifier. The saturable feature reduces the current transformer turns. Inherent dynamic gate voltage controlled by saturable current transformer reduces gate loss in the MOSFET. A novel driving circuit is proposed for accurate turn off time. It reduces loss significantly. This synchronous rectifier is completely self-contained which can replace the rectifier diode as a drop in replacement. It is insensitive to parasitic inductance. In order to explain the current transformer saturable, a model of saturable current transformer is proposed. A prototype demonstrates the advantages of the proposed current driven synchronous rectifier. Furthermore, a novel integrated synchronous rectifier is presented which provides a more compact system. The synchronous rectifier current transformer is integrated with the main transformer which reduces the number of circuit joints in power path. Each soldering joint generates significance loss in power converter. A pair of 0.5mΩ soldering joint in 25A current path produces 0.62W loss. The placement of the integrated current transformer is important. A criterion for the placement of the current transformer within the main transformer is to avoid interference to the current transformer from the magnetic flux of the main transformer. Thus, a placement method to integrate the current transformer into the main transformer is proposed. An integrated current transformer model is suggested to explain the operation of the integrated synchronous rectifier. A prototype demonstrates the advantages of the integrated synchronous rectifier. / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

High power conversion efficiency is desirable in power supplies. Design optimization of on-line power converter is presented in this thesis. High efficiencies over a wide load range, for example 20%, 50% and 100% load, are often required. It is a challenge for on-line pulse-width modulation (PWM) converters to maintain good efficiencies with light load as well as full load. A two-stage multi-objective optimization procedure is proposed to optimization power converter efficiencies at 20%, 50% and 100% load. Two-FET forward prototype converters are built to verify the optimization results. The LLC (abbreviation of two resonant inductor L and one resonant capacitor C ) series resonant converter can provide high power conversion efficiency because of the resonant nature and soft switching. The design of LLC resonant converter is more difficult than that of PWM converters since the LLC resonant converter has many resonant modes. Furthermore, the LLC resonant converter does not have analytical solution for its resonant operation. In this thesis, a systematic optimization procedure is proposed to optimize LLC series resonant converter efficiency. A mode solver technique is developed to solve LLC resonant converter operations. The proposed mode solver employs non-linear programming techniques to solve a set of LLC state equations and determine the resonant modes. Loss models are provided which serve as the objective-function to optimize converter efficiency. Optimization results show outstanding efficiency performance and experimental agreement with optimization. The optimization work extends to the LLC resonant converter with power factor correction (PFC) circuits where the effect of LLC converter input voltage variation cased by the PFC circuit is considered. Detail comparisons of PWM converter and LLC resonant converter loss profiles are also presented. The reasons that LLC resonant converter has higher efficiency are given and supported by quantitative data. Converter lifetime is highly related to component losses and temperature. The lifetime analysis is presented. The analysis reveals that the LLC resonant converter output capacitor is the weakest component concerning life. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

There is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored. First, I propose a mostly-digital time-based oversampling delta-sigma (∆Σ) ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects. In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) processes. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and ∼50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm² , while the second generation ADC core occupies 0.0192 mm² . The two prototypes can be categorized as some of the smallestarea modulators in the literature. Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored over traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area. / text

M. Tech. Electrical Engineering. / Aims to analyze, design and develop a transformer-less 5-level converter topology with an improvement in the output waveform and to investigate its suitability for AC/DC, DC/AC and back-to-back configuration.