Switch-mode power supplies (SMPS's) not only convert energy, they also consume it. Typical operational efficiencies are approximately 25 to 60% for linear power supplies, and approximately 50-90% for switching power supplies. This means that products whose end-use electronics are dc, such as televisions and DVD players, could consume 50% less power when operating if the power supply were upgraded from 40% efficiency to 80% efficiency. Savings can occur not only from using SMPS's instead of linear power supplies, but also from specifying highly efficient switching power supplies. In many cases, efficiencies are still lagging to keep costs down, since the power consumption is considered to be relatively low (40W-700W range). Over time, however, efficiency improvement strategies will pay back based on the cost of energy. Therefore three common flyback converter topologies have been studied through this thesis in the Low (15W), Medium (40W), and High (150W) Power levels. Efficiency analysis on the three power level topologies showed that the greatest opportunity for efficiency improvement existed in the 40W (medium power) topology. Efficiency improvement and measurement approaches are investigated and an optimized medium-power flyback converter is proposed and implemented resulting in an efficiency improvement from 57.8% to 83.6%. / Graduation date: 2004

Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent current, minimal external components and low cost. In this thesis, two step-down switched capacitor DC/DC converters are designed. One has the fixed output options 1.5V, 1.8V and 2.0V. The other one has the output 1.2V. These two converters are implemented in 0.5��m CMOS process through National Semiconductor Corporation. The design is verified by the circuit-level simulations, and design issues are discussed. / Graduation date: 2004

A differential current-mode track-and-hold (T/H) amplifier is used to sample an analog input signal. A new closed-loop current-mode architecture has been developed that overcomes the stability problems associated with closed-loop architectures. The T/H circuit has been fabricated in a 0.35-��m quad-metal, double-poly CMOS process. The measured total harmonic distortion (THD) is -81dB and -65dB with an input signal frequency of 100KHz and 10MHz, respectively. This is the best performance reported to date for a CMOS implementation. / Graduation date: 2003

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999

The advance of digital IC technology has been very fast, as shown by rapid development of DSP, digital communication and digital VLSI. Within electronic signal processing, analog-to-digital conversion is a key function, which converts the analog signal into digital form for further processing. Recently, low-voltage and low-power have become also an important factors in IC development. This thesis investigates some novel techniques for the design of low-power high-performance A/D converters in CMOS technology, and the non-ideal switched-capacitor effects of (SC) circuits. A new successive-approximation A/D converter is proposed with a novel error cancellation scheme. This A/D converter needs only a simple opamp, a comparator, and a few switches and capacitors. It can achieve high resolution with relative low power consumption. A new ratio-independent cyclic A/D converter is also proposed with techniques to compensate for the non-ideal effects. The implementation include a new differential sampling that is used to achieve ratio-independent multiple-by-two operation. Extensive simulations were performed to demonstrate the excellent performance of these data converters. / Graduation date: 1999

An AC/AC converter has been designed and implemented for the purpose of providing a modular drive system with a Brushless Doubly-Fed Machine (BDFM.) This converter is to be used in laboratory testing and also as part of a demonstration system in the field. All hardware needed to start and run the BDFM is now consolidated into a single NEMA standard frame electrical equipment box. This allows easy transportation and setup of the drive system, and will enable the BDFM drive system to be directly compared with existing induction machine based drive systems. Converter subsystem overviews in the body of the text and comprehensive schematics in the appendices of this thesis describe all circuitry included in the drive system. Sufficient construction detail is given to allow for duplication of this converter by qualified technical personnel. While not tailored for mass production, this converter may provide a starting point for a commercially viable design. / Graduation date: 1998

Multi-level decision feedback equalization (MDFE) is a sampled signal processing technique for data recovery from magnetic recording channels which use the 2/3(1,7) run length limited code. The key adaptive feedback loops in MDFE are those which perform the timing recovery, gain recovery, dc offset detection, and adaptive equalization of the feedback equalizer. The algorithms used by these adaptive loops are derived from the channel error which is the deviation of the equalized signal from its ideal value. It is advantageous to convert this error signal to a digital value using a flash analog-to-digital converter (flash ADC) to simplify the implementation of the adaptive loops. In this thesis, a scheme to place the thresholds of the flash ADC is presented. The threshold placement has been optimized based on the steady-state probability density function (pdf) of the signal to be quantized. The resolution constraints imposed by this quantization scheme on the adaptive loops has been characterized. As the steady-state assumption for the signal to be quantized is not valid during the transient state of the adaptive loops, the loop transients with this quantization scheme have been analyzed through simulations. The conditions under which the channel can recover from a set of start-up errors and converge successfully into steady-state have been specified. The steady-state channel performance with the noise introduced by the iterative nature of the adaptive loops along with this quantization scheme has also been verified. / Graduation date: 1997

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instruments which convert IF, or even RF, analog signals directly to digital form. This thesis presents a method used to analyze and synthesize continuous-time delta-sigma modulators for given specifications. A fourth-order prototype continuous-time bandpass delta-sigma modulator employing g[subscript m]-LC resonator structure is demonstrated on a PCB board and measurement results corroborate the theory. To allow the construction of very high performance delta-sigma modulators, this thesis presents an architecture for a multibit DAC constructed from unit elements which shapes element mismatches. Theoretical analysis and simulation shows that this architecture greatly increases the noise attenuation in the band-of-interest and facilitates the use of multibit quantization in delta-sigma modulators. The methods presented in this thesis will allow high-frequency wideband bandpass delta-sigma modulators to be constructed. / Graduation date: 1996

A transient code (TFETC) for calculating the temperature distribution throughout the radial and axial positions of a thermionic fuel element (TFE) has been successfully developed. It accommodates the variations of temperatures, thermal power, electrical power, voltage, and current density throughout the TFE as a function of time as well as the variations of heat fluxes arising from radiation, conduction, electron cooling, and collector heating. The thermionic fuel element transient code (TFETC) is designed to calculate all the above variables for three different cases namely: 1) Start-up; 2) Loss of flow accident; and 3) Shut down. The results show that this design is suitable for space applications and does not show any deficiency in the performance. It enhances the safety factor in the case of a loss of flow accident (LOFA). In LOFA, it has been found that if the mass flow rate decreases exponentially by a -0.033t, where t is a reactor transient time in seconds, the fuel temperature does not exceed the melting point right after the complete pump failures but rather allows some time, about 34 seconds, before taking an action. If the reactor is not shut down within 34 seconds, the fuel temperature may keep increasing until the melting point of the fuel is attained. On the other hand, the coolant temperature attains its boiling point, 1057 ��K, in the case of a complete pump failure and may exceed it unless a proper action to trip the reactor is taken. For 1/2, 1/3, and 1/4 pump failures, the coolant temperatures are below the boiling point of the coolant. / Graduation date: 1994

Graduation date: 1994