Este trabalho apresenta algumas estratégias de controle das malhas de rastreamento de tensão e corrente no lado CA de conversores do tipo fonte de tensão com filtro L ou LC. A topologia escolhida para o controle de tensão CA do inversor é a de duas malhas de controle em cascata: malha de tensão e malha de corrente, sendo esta última mais interna no sistema de controle. A metodologia de trabalho utilizada consiste na modelagem do sistema (sistema controlado e controladores), ajuste dos parâmetros do controlador, simulação computacional do sistema \"inversor + controlador\", implementação de alguns controladores propostos utilizando um DSP e testes em um sistema real com inversor. O estudo das técnicas de controle concentra-se inicialmente na estratégia de realimentação de dois estados no domínio de tempo contínuo, evoluindo para estratégias em tempo discreto que consideram o atraso na atuação do inversor devido ao tempo de cálculo do algoritmo de controle. Em tempo discreto, são analisados controladores preditivos para as malhas de tensão e corrente, bem como o emprego de controladores Proporcional-Integral (PI) na malha de tensão. Os dois últimos controladores são testados em um inversor PWM de baixa potência para diversos tipos de carga, com tensão de referência de inversor senoidal em 60Hz e referência contendo harmônicas. / This work presents some control strategies to achieve voltage and current tracking at the AC side of Voltage Source Converters with L or LC output filters. The topology of voltage control is the Multi-loop control with two loops: Voltage (outer loop) and Current Loop (inner loop). The proposed methodology consists in modeling the control system (plant and controllers), tuning of the controller parameters, simulating the complete system including inverter and controller, implementation of the proposed control strategies on a Digital Signal Processor (DSP) and tests in a power converter. The thesis is initially focused on a state variable continuous time controller with two states and then discrete-time strategies which consider the actuation delay due to the time required to evaluate the control algorithm are studied. In these discrete-time models, predictive controllers in voltage and current loops are analyzed, as well as the use of Proportional- Integral (PI) controllers in the Voltage Loop. These two last control topologies are tested in a low-power inverter for several load conditions with sinusoidal 60Hz inverter reference voltage and with harmonic distortion in the inverter reference voltage.

Este trabalho apresenta as principais topologias de conversores multinível descritos na literatura. É feita uma revisão bibliográfica, apresentando as vantagens e as limitações de cada topologia. A seguir são apresentados os métodos mais usuais de modulação para conversores multinível, bem como os campos de aplicação na indústria e em sistemas de potência As associações de conversores baseadas em conversores do tipo ponte completa monofásica foram escolhidas para um estudo mais detalhado. Para estas topologias são apresentados detalhes sobre as respectivas estratégias de controle e modulação. Inicialmente são apresentados os detalhes da ponte completa monofásica com tensão de saída modulada em PWM com dois e três níveis. A seguir são estudadas as associações série e paralela com barramentos CC isolados. O estudo da associação paralela com barramento CC único é a principal contribuição desta dissertação. Para esta topologia são propostas algumas estratégias de controle. Para todos estes casos são apresentados resultados de simulação e experimentais obtidos com inversores operando com potência reduzida, controlados por DSP. / This work presents the main multilevel converter topologies described in the literature. A bibliography revision is presented, showing the advantages and limitations of each topology. The most usual multilevel modulation methods are also presented, as well as their fields of application in the industry as well as in power systems. The one phase full bridge and its associations were chosen for detailed study. For this family of topologies, this dissertation presents details about control and modulation strategies. Initially, details about the one phase full bridge with two and three levels PWM modulated output voltage are presented. Next, the series association is analyzed, followed by the parallel with isolated DC link. The study of parallel connection with a single DC Link is the mainly contribution of this dissertation. For this topology are proposed some control strategies. For all these cases, simulation and experimental results (with, small scale prototype controlled by DSP) are presented.

In this thesis, a digital-PID-control single-inductor triple-output (SITO) DC-DC converter is realized in AMS 0.35mum CMOS technology. The size of the chip is about 1600 mum x 1700 mum. To improve load current and reduce cross regulation, a Pre-Sub-Period inductor-current regulation is proposed. Based on the maximum duty cycle limiter, an adaptive inductor current adjustment is realized when the duty cycle of the digital PWM signal is larger than the set maximum duty cycle. By an optimized phase control sequence, the S&H stages of the feedback switching and ADC are controlled to on/off with a minimized delay time. Moreover, the control sequence can virtually remove the setting time. / Multiple voltage supplies are necessary to satisfy the different voltage supply requirements of the different on-chip blocks to reduce power consumption in modem electronic devices, such as the modem embedded systems, the portable devices, personal computing devices and wireless communications and imaging systems. For example, WiMAX transmitter includes different sub-blocks: Baseband processor, IQ modulator and power amplifier. Different blocks should operate with the different power supply voltages to satisfy the different requirements. / Single-input multiple-output DC-DC converter is presented to provide the different voltage supplies and reduce the cost on the elements such as the inductor on PCB and save PCB area. Meanwhile, to remove cross regulation and improve load driving capability, the DC-DC converter should operate in the pseudo-continuous mode/discontinuous mode (P-CCM/DCM). However, in the previous designs, the DC current in the inductor is fixed. When the load becomes heavy enough, cross regulation will significantly affect across the different sub-converters. / Jia, Jingbin. / "December 2009." / Adviser: KaNang Leung Alex. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 121-124). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Liu, Renting. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 40-46). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Related Work and System Overview --- p.6 / Chapter 2.1 --- Previous Work in Blur Analysis --- p.6 / Chapter 2.1.1 --- Blur detection and estimation --- p.6 / Chapter 2.1.2 --- Image deblurring --- p.8 / Chapter 2.1.3 --- Low DoF image auto-segmentation --- p.14 / Chapter 2.2 --- System Overview --- p.15 / Chapter 3 --- Blur Features and Classification --- p.18 / Chapter 3.1 --- Blur Features --- p.18 / Chapter 3.1.1 --- Local Power Spectrum Slope --- p.19 / Chapter 3.1.2 --- Gradient Histogram Span --- p.21 / Chapter 3.1.3 --- Maximum Saturation --- p.24 / Chapter 3.1.4 --- Local Autocorrelation Congruency --- p.25 / Chapter 3.2 --- Classification --- p.28 / Chapter 4 --- Experiments and Results --- p.29 / Chapter 4.1 --- Blur Patch Detection --- p.29 / Chapter 4.2 --- Blur degree --- p.33 / Chapter 4.3 --- Blur Region Segmentation --- p.34 / Chapter 5 --- Conclusion and Future Work --- p.38 / Bibliography --- p.40 / Chapter A --- Blurred Edge Analysis --- p.47

Tong, Fung Ling. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 94-96). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgement --- p.iii / Table of Contents --- p.iv / List of Figures --- p.vii / List of Tables --- p.x / Chapter Chapter 1 - --- Introduction --- p.1 / Chapter Chapter 2 - --- State of the art in Vision-based Localization --- p.6 / Chapter 2.1 --- Extended Kalman Filter-based Localization --- p.6 / Chapter 2.1.1 --- Overview of the EKF algorithm --- p.6 / Chapter 2.1.2 --- Process of the EKF-based localization algorithm --- p.8 / Chapter 2.1.3 --- Recent EKF-based vision-based localization algorithms --- p.10 / Chapter 2.1.4 --- Advantages of the EKF-based localization algorithms --- p.11 / Chapter 2.1.5 --- Disadvantages of the EKF-based localization algorithm --- p.11 / Chapter 2.2 --- Monte Carlo Localization --- p.12 / Chapter 2.2.1 --- Overview of MCL --- p.12 / Chapter 2.2.2 --- Recent MCL-based localization algorithms --- p.14 / Chapter 2.2.3 --- Advantages of the MCL-based algorithm --- p.15 / Chapter 2.2.4 --- Disadvantages of the MCL-based algorithm --- p.16 / Chapter 2.3 --- Summary --- p.16 / Chapter Chapter 3 - --- Vision-based Localization as an Optimization Problem --- p.18 / Chapter 3.1 --- "Relationship between the World, Camera and Robot Body Coordinate System" --- p.18 / Chapter 3.2 --- Formulation of the Vision-based Localization as an Optimization Problem --- p.21 / Chapter 3.3 --- Summary --- p.26 / Chapter Chapter 4 - --- Existing Search Algorithms --- p.27 / Chapter 4.1 --- Overview of the Existing Search Algorithms --- p.27 / Chapter 4.2 --- Search Algorithm for the Proposed Objective Function --- p.28 / Chapter 4.3 --- Summary --- p.30 / Chapter Chapter 5 - --- Proposed Vision-based Localization using Genetic Algorithm --- p.32 / Chapter 5.1 --- Mechanism of Genetic Algorithm --- p.32 / Chapter 5.2 --- Formation of Chromosome --- p.35 / Chapter 5.3 --- Fitness Function --- p.39 / Chapter 5.4 --- Mutation and Crossover --- p.40 / Chapter 5.5 --- Selection and Stopping Criteria --- p.42 / Chapter 5.6 --- Adaptive Search Space --- p.44 / Chapter 5.7 --- Overall Flow of the Proposed Algorithm --- p.46 / Chapter 5.8 --- Summary --- p.47 / Chapter Chapter 6 - --- Experimental Results --- p.48 / Chapter 6.1 --- Test Robot --- p.48 / Chapter 6.2 --- Simulator --- p.49 / Chapter 6.2.1 --- Camera states simulation --- p.49 / Chapter 6.2.2 --- Oscillated walking motion simulation --- p.50 / Chapter 6.2.3 --- Input images simulation --- p.50 / Chapter 6.3 --- Computer for simulations --- p.51 / Chapter 6.4 --- Position and Orientation errors --- p.51 / Chapter 6.5 --- Experiment 1 一 Feature points with quantized noise --- p.53 / Chapter 6.5.1 --- Setup --- p.53 / Chapter 6.5.2 --- Results --- p.56 / Chapter 6.6 --- Experiment 2 一 Feature points added with Gaussian noise --- p.62 / Chapter 6.6.1 --- Setup --- p.62 / Chapter 6.6.2 --- Results --- p.62 / Chapter 6.7 --- Experiment 3 一 Noise reduction performance of the adaptive search space strategy --- p.77 / Chapter 6.7.1 --- Setup --- p.77 / Chapter 6.7.2 --- Results --- p.79 / Chapter 6.8 --- Experiment 4 一 Comparison with benchmark algorithms --- p.83 / Chapter 6.8.1 --- Setup --- p.83 / Chapter 6.8.2 --- Results --- p.85 / Chapter 6.9 --- Discussions --- p.88 / Chapter 6.10 --- Summary --- p.90 / Chapter Chapter 7- --- Conclusion --- p.91 / References --- p.94

Random Telegraph Signal (RTS) noise is a random noise source defined by discrete and metastable changes in the magnitude of a signal. Though observed in a variety of physical processes, RTS is of particular interest to image sensor fabrication where progress in the suppression of other noise sources has elevated its noise contribution to the point of approaching the limiting noise source in scientific applications. There have been two basic physical sources of RTS noise reported in image sensors. The first involves a charge trap in the oxide layer of the source follower in a CMOS image sensor. The capture and emission of a charge changes the conductivity across the source follower, altering the signal level. The second RTS source in image sensors has been reported in CCD and CMOS architectures and involves some metastability in the structure of the device within the light collection area. A methodology is presented for the analysis of RTS noise. Utilizing wavelets, a time-based signal has white noise removed, while RTS transitions are preserved. This allows for the simple extraction of RTS parameters, which provide valuable insight into defects in semiconductor devices. The scheme is used to extract RTS transition amplitudes and time constants from radiation damaged CMOS image sensor pixels. Finally, the generation of ionizing radiation induced RTS centers is investigated and discussed. Surprisingly, the number of RTS centers does not scale linearly with absorbed dose, but instead follows a quadratic dependence. The implications and possible mechanisms behind the generation of these RTS centers are discussed.

The frequency response analysis of switched networks plays a very important part in designing various kinds of power converter circuits. In this thesis two frequency response techniques for analyzing switching power converters are discussed. One method provides a mathematical description which treats the converter as a periodic time varying system. A linearized small signal model is subsequently derived. The major part of the thesis concentrates on this accurate exact small-signal technique. The derivation involves state space representation and the use of the time varying transfer function. A Fourier analysis is performed to show the relationship between the frequency response of the network and the time varying transfer function. The obtained expressions are in closed form. The method has proven to be exact. The complexity of this technique is overcome by automating its derivation in conjunction with a circuit simulator. An alternative method, relying only on a sampled-data representation, is also derived, which provides a less complicated algorithm. However the accuracy of this method suffers, particularly at high frequencies. The accuracy of the exact small-signal technique is verified by experimentation.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter needs only one op-amp, 4 comparators and 3 capacitors. Power reduction techniques are discussed with respect to the biosensor and the ADC. The ADC is designed for fabrication in a CMOS 0.18μm process. / Graduation date: 2004

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004