Este trabalho apresenta algumas estratégias de controle das malhas de rastreamento de tensão e corrente no lado CA de conversores do tipo fonte de tensão com filtro L ou LC. A topologia escolhida para o controle de tensão CA do inversor é a de duas malhas de controle em cascata: malha de tensão e malha de corrente, sendo esta última mais interna no sistema de controle. A metodologia de trabalho utilizada consiste na modelagem do sistema (sistema controlado e controladores), ajuste dos parâmetros do controlador, simulação computacional do sistema \"inversor + controlador\", implementação de alguns controladores propostos utilizando um DSP e testes em um sistema real com inversor. O estudo das técnicas de controle concentra-se inicialmente na estratégia de realimentação de dois estados no domínio de tempo contínuo, evoluindo para estratégias em tempo discreto que consideram o atraso na atuação do inversor devido ao tempo de cálculo do algoritmo de controle. Em tempo discreto, são analisados controladores preditivos para as malhas de tensão e corrente, bem como o emprego de controladores Proporcional-Integral (PI) na malha de tensão. Os dois últimos controladores são testados em um inversor PWM de baixa potência para diversos tipos de carga, com tensão de referência de inversor senoidal em 60Hz e referência contendo harmônicas. / This work presents some control strategies to achieve voltage and current tracking at the AC side of Voltage Source Converters with L or LC output filters. The topology of voltage control is the Multi-loop control with two loops: Voltage (outer loop) and Current Loop (inner loop). The proposed methodology consists in modeling the control system (plant and controllers), tuning of the controller parameters, simulating the complete system including inverter and controller, implementation of the proposed control strategies on a Digital Signal Processor (DSP) and tests in a power converter. The thesis is initially focused on a state variable continuous time controller with two states and then discrete-time strategies which consider the actuation delay due to the time required to evaluate the control algorithm are studied. In these discrete-time models, predictive controllers in voltage and current loops are analyzed, as well as the use of Proportional- Integral (PI) controllers in the Voltage Loop. These two last control topologies are tested in a low-power inverter for several load conditions with sinusoidal 60Hz inverter reference voltage and with harmonic distortion in the inverter reference voltage.

Tang, Xian. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the“Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the“Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within ±1 LSB.

This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC has been realized in a 0.6um digital CMOS process. The architecture is based on a 1.5-b per stage structure utilizing digital correction for the first six stages. A differeintial switched capacitor circuit consisting of a cascode gm-c op-amp with 250MHz of bandwidth is used for sampling and amplification in each stage. Comparators with an internal offset voltage are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by measuring the offset and gain of each of the first six stages using subsequent stages. The measured values are used to calculate digtal values the compensate for the inaccuracies of the analog pipeline. Corrected digital values for each stage are stored in the pipeline and used to create corrected output codes. Errors caused by measuring the first six stages using uncalibrated stages are minimized by using extra switching circuitry during calibration.

A multiple-input-multiple-output, or MIMO, receiver receives multiple data streams in the same frequency band at the same time, significantly improving spectral efficiency. It has to preserve all the antenna aperture information and use it to deliver as many data streams as the antenna count. As the number of antennas increases, implementing a MIMO receiver system in the analog domain becomes difficult. A digital MIMO receiver architecture that digitizes all the antenna inputs on the element level offers multiple advantages. Digital MIMO signal processing is flexing and powerful. Complex space-time array processing is supported and so is digital array calibration. Therefore, the digital MIMO receiver architecture has become the most promising architecture for future massive MIMO systems. However, the digital MIMO receiver architecture has a disadvantage, namely that the spatial selectivity feature is missing in the RF/analog domain. At the target frequency band, multiple spatial signals can arrive at the antenna array at different power levels. Conventional spectral filtering is ineffective at in-band frequency so all the spatial signals have to co-exist in all the receiver elements and the following analog-to-digital converters (A/Ds). The instantaneous dynamic range required for these RF/analog and mixed-signal circuits will be limited by the strongest spatial signal on the upper bound, and the weakest spatial signal on the lower bound. A high instantaneous dynamic range requirement directly translates to high power consumption and high cost. Therefore, the recovery of spatial selectivity in the RF/analog domain is necessary. The first thrust toward recovering RF/analog spatial selectivity in a digital MIMO receiver is the scalable spatial notch suppression technique. Knowing the direction of a strong spatial blocker, a spatial notch, instead of beams, can be synthesized to the blocker direction to filter it out. This means that all the analog baseband outputs will show high conversion gains to signals from all directions but one, namely the blocker direction. In this way, high sensitivity is preserved in most directions to receiver multiple weak spatial signals simultaneously, which will be digitized, and separated in the digital domain. In the blocker direction, a low conversion gain filters the blocker out, preventing it from demanding high dynamic range for all of the RF/analog circuits and the A/Ds. In order to synthesize the scalable spatial notch, a spatial notch filter (SNF) is designed to provide lower input impedance in the blocker direction and high impedance in other directions. Using this spatially modulated impedance to load a current mode receiver leads to spatially modulated conversion gain. A transparent RF front-end translates this impedance to the antenna interface to achieve spatial notch suppression right at the antennas. A feedforward spatial notch canceler (FF SNC) uses the available isolated blocker information to improve spatial suppression ratio. The spatial notch suppression is scalable through a baseband node, allowing the tiling of multiple ICs on the same PCB for larger scale MIMO systems. A prototype receiver array was implemented with a 65nm CMOS process. Experimental results showed 32dB steerable spatial notch suppression, more than 19db of suppression inside the notch direction across all frequencies. In-band output-referred IP3 was improved from -10dBV to +24dBV, from outside to inside the notch direction, and IIP3 was also improved from +11dBm to +18dBm. Single-element equivalent double-sideband noise figure (NFDSB,eq) was 2.2 to 4.6dB across the 0.1 to 1.7GHz operating frequency range, also showing an improvement compared to other multi-antenna receivers at similar frequency ranges. A second thrust is an RF/analog arbitrary spatial filtering receiver. Instead of filtering out strong spatial blockers, a more general and robust way to recover spatial selectivity is to impose an arbitrary spatial response that adaptively equalizes the power levels of all the spatial signals. In this way, all the spatial signals should have the same power level when reaching the A/Ds, allowing the use of low-power A/Ds with low dynamic ranges, which are essential for the realization of the digital massive MIMO solution. Such an arbitrary spatial filtering response requires the ability to synthesize multiple spatial notches that can be independently steered, the depth of the notches free adjusted. In addition, a few performance metrics need to be improved based on the first work. Spatial suppression ratio was limited by the lack of magnitude control in the first work. In-band in-notch linearity performance was limited by the use of voltage mode gyrators that requires a band-limiting high-impedance node, which also limits spatial suppression bandwidth. Also, the antenna array dimensions scale inversely with operating frequency. So pushing the receiver array to work at higher frequency is also desired. Toward these goals, a 65nm CMOS prototype receiver array was implemented. Wideband current-mode receiver front-ends that consist of inverter-based LNTAs and passive mixers can work up to 3.1GHz. A baseband current-mode beamformer can synthesize virtual grounds at the output nodes in the target notch directions, providing not only an arbitrary spatial response but also an baseband input impedance that is also spatially modulated, allowing spatial filtering at the LNTA output nodes. Current mode operation avoids the use of band-limiting high impedance nodes for strong spatial signals, leading to superior linearity and wideband spatial suppression. This 4-element prototype measured more than 50dB of spatial suppression ratios with single-notch settings across all measured directions. Up to three notches can be synthesized, each of which can be independently steered and its depth freely adjusted. An in-band OIP3 of +34dBV was measured, 10dB higher than the first work, due to the current mode operation. A 20dB suppression bandwidth of 320MHz, or equivalently 64% was measured, more than 20× improvement than the first work, also due to the current mode operation. On a separate note, an ultra-wideband LNTA was also designed for an RF channelizing receiver work. This two-stage LNTA makes use of a gm-boosted current mirror structure to harness the linearity advantage of a current mirror, the low-noise input matching of the feedback structure, the high transconductance gain of a two-stage structure and an ultra-wideband input matching advantage of a gyrator. The implemented 65nm CMOS prototype is fully integrated, and provides 242mS peak transconductance gain over 0.6-9.6GHz operating frequency range. It achieves 4.5dB of NF and +6.5dBm of IIP3. In summary, RF/analog spatial selectivity can be recovered in innovative methods to relax the dynamic range requirement for all the RF/analog circuits together with the following A/Ds in a digital MIMO receiver. The scalable spatial notch suppression technique and the arbitrary spatial filtering technique allow the use of low-power A/Ds, which are essential for truly massive MIMO systems with manageable power consumption.

Chi-Hong, Chan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 114-117). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiii / Chapter 1. --- Introduction --- p.1 / Chapter 1.1. --- System on a Chip (SoC) Design Challenges --- p.1 / Chapter 1.2. --- Research Objective --- p.3 / Chapter 1.3. --- Thesis Organization --- p.3 / Chapter 2. --- Fundamentals of CMOS Current Mode A/D converters --- p.5 / Chapter 2.1. --- Overview --- p.5 / Chapter 2.2. --- Current Mode Signal Processing --- p.5 / Chapter 2.2.1. --- Voltage Mode Circuit Design Technique --- p.5 / Chapter 2.2.2. --- Current Mode Circuit Design Technique --- p.6 / Chapter 2.2.3. --- First Generation (FG) SI Memory Cell vs. Second Generation (SG) SI Memory Cell --- p.7 / Chapter 2.3. --- Ideal Nyquist Rate A/D converters --- p.9 / Chapter 2.4. --- Static Performance Parameters --- p.13 / Chapter 2.4.1. --- Differential Non-Linearity (DNL) --- p.13 / Chapter 2.4.2. --- Integral Non-Linearity (INL) --- p.13 / Chapter 2.5. --- Performance Parameters in Frequency Domain --- p.15 / Chapter 2.5.1. --- Signal-to-Noise and Distortion Ratio (SNDR) --- p.16 / Chapter 2.5.2. --- Effective Number of Bits (ENOB) --- p.16 / Chapter 2.5.3. --- Spurious Free Dynamic Range (SFDR) --- p.16 / Chapter 3. --- Proposed Current Mirror Memory Cell (CMMC) --- p.18 / Chapter 3.1. --- Overview --- p.18 / Chapter 3.2. --- Working Principle of CMMC --- p.18 / Chapter 3.3. --- CMMC vs. FG SI Cells --- p.20 / Chapter 3.4. --- Analog Delay Cell Implementation using the two kinds of memory cells --- p.21 / Chapter 3.4.1. --- Delay Cell Implementation by FG Memory Cells --- p.22 / Chapter 3.4.2. --- Delay Cell Implementation by CMMC --- p.23 / Chapter 3.4.3. --- Simulation Results --- p.24 / Chapter 3.5. --- Conclusion --- p.27 / Chapter 4. --- Architectural Design of the 12-Bit CMOS A/D Converter --- p.28 / Chapter 4.1. --- Overview --- p.28 / Chapter 4.2. --- The Floating Analog-to-Digital Converter --- p.28 / Chapter 4.3. --- Conversion Algorithm --- p.32 / Chapter 4.4. --- Accuracy Considerations Due to Circuit Non-Idealities --- p.34 / Chapter 4.4.1. --- Gain Error of Residual Generator --- p.34 / Chapter 4.4.2. --- Offset Error of Residual Generator --- p.36 / Chapter 4.5. --- Speed Consideration --- p.36 / Chapter 4.6. --- Power Consumption vs. No. of Bits per Stage --- p.38 / Chapter 4.7. --- Final Architectural Design --- p.40 / Chapter 5. --- A/D Converter Implementation using CMMC --- p.41 / Chapter 5.1. --- Overview --- p.41 / Chapter 5.2. --- Current Sample-and-Hold --- p.41 / Chapter 5.2.1. --- Signal Independent CFT Cancellation --- p.43 / Chapter 5.2.2. --- Signal Dependent CFT Cancellation --- p.44 / Chapter 5.2.3. --- Complete CFT Cancellation --- p.45 / Chapter 5.2.4. --- CFT Cancellation by Transmission Gate --- p.45 / Chapter 5.2.5. --- CFT Cancellation by Dummy Switches --- p.47 / Chapter 5.3. --- Common Mode Feed Forward (CMFF) --- p.48 / Chapter 5.4. --- Differential Current Comparator --- p.52 / Chapter 5.4.1. --- Regenerative Latch --- p.53 / Chapter 5.4.2. --- Pre-amplifier --- p.54 / Chapter 5.5. --- Residual Generator --- p.55 / Chapter 5.6. --- Thermometer to Binary code Decoder --- p.57 / Chapter 6. --- Layout Considerations --- p.59 / Chapter 6.1. --- Overview --- p.59 / Chapter 6.2. --- Process Introduction --- p.59 / Chapter 6.3. --- Common Centroid Layout --- p.60 / Chapter 6.4. --- The Design of Power Supply Rails --- p.63 / Chapter 6.5. --- Shielding --- p.64 / Chapter 6.6. --- Layout of the whole design --- p.65 / Chapter 7. --- Simulation Results --- p.67 / Chapter 7.1. --- Overview --- p.67 / Chapter 7.2. --- Simulation Results of the Current Sample-and-Hold --- p.67 / Chapter 7.3. --- Simulation Results of the Differential Current Comparator --- p.70 / Chapter 7.4. --- Simulation Results of the overall ADC using One-Stage Simulation Result --- p.71 / Chapter 7.5. --- Power Simulation of the Overall 12-Bit ADC --- p.75 / Chapter 7.6. --- Summary --- p.78 / Chapter 8. --- Measurement Results --- p.79 / Chapter 8.1. --- Overview --- p.79 / Chapter 8.2. --- PCB Design Consideration --- p.79 / Chapter 8.3. --- Measurement Setup --- p.82 / Chapter 8.4. --- Measurement Result --- p.84 / Chapter 8.4.1. --- Static Parameters --- p.84 / Chapter 8.4.2. --- Frequency Domain Measures --- p.85 / Chapter 8.5. --- Discussion --- p.90 / Chapter 9. --- Conclusion --- p.95 / Chapter 9.1. --- Research Methodology of this Project --- p.95 / Chapter 9.2. --- Comparison between Voltage Mode and Current Mode Circuit --- p.97 / Chapter 9.3. --- Contribution of this Project --- p.98 / Chapter A. --- Appendices --- p.99 / Chapter A.I. --- Small Signal Analysis on CMMC and FG Memory Cell --- p.99 / Chapter A.II. --- The ESD Protection on the ADC --- p.102 / Chapter A.III. --- The Histogram Test to determine the DNL and INL of ADC --- p.104 / Chapter A.IV. --- Measurement Result of a Commercially Available ADC AD7820 --- p.106 / Chapter A.V. --- Pin Assignment of the Current Mode ADC --- p.109 / Chapter A.VI. --- Schematics of the Current Mode ADC --- p.111 / Chapter A.VII. --- The Chip Micrograph --- p.113 / Bibliography --- p.114

by Cheng Wang-tung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 97-99). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.i / Acknowledgements --- p.ii / Table of Contents --- p.iii / List of Figures --- p.vii / List of Tables --- p.xi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Objective --- p.4 / Chapter 1.3 --- Outline --- p.4 / Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6 / Chapter 2.3 --- Theory of ΣΔ modulation --- p.6 / Chapter 2.3.1 --- Quantization noise --- p.7 / Chapter 2.3.2 --- Oversampling --- p.8 / Chapter 2.3.3 --- Noise Shaping --- p.9 / Chapter 2.3.4 --- Performance Parameter --- p.11 / Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11 / Chapter 2.3.6 --- Case Study --- p.12 / Chapter 2.3.6.1 --- Transfer Function --- p.12 / Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13 / Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14 / Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15 / Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18 / Chapter 2.5.1 --- Quadrature signal --- p.18 / Chapter 2.5.2 --- I/Q Modulation --- p.19 / Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21 / Chapter 2.6.1 --- High Level Simulation --- p.23 / Chapter 2.6.2 --- Discussion --- p.26 / Chapter 2.7 --- Summary --- p.27 / Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28 / Chapter 3.2.1 --- Principle of Operation --- p.30 / Chapter 3.3 --- Justification of the Proposed Idea --- p.35 / Chapter 3.4 --- Summary --- p.37 / Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Design of ΣΔ Modulator --- p.39 / Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40 / Chapter 4.3 --- Design of Operational Amplifier --- p.45 / Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45 / Chapter 4.3.2 --- Common Mode feedback --- p.47 / Chapter 4.3.3 --- Bias Circuit --- p.49 / Chapter 4.3.4 --- Simulation Results --- p.50 / Chapter 4.4 --- Design of Comparator --- p.54 / Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54 / Chapter 4.4.2 --- Simulation Results --- p.55 / Chapter 4.5 --- Design of Clock Generator --- p.56 / Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57 / Chapter 4.5.2 --- Simulation Results --- p.58 / Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59 / Chapter 4.7 --- Simulation Results --- p.61 / Chapter 4.7.1 --- Proposed Architecture --- p.62 / Chapter 4.7.2 --- Traditional Architecture --- p.62 / Chapter 4.8 --- Summary --- p.63 / Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Common-Centroid Structure --- p.65 / Chapter 5.3 --- Shielding Technique --- p.67 / Chapter 5.3.1 --- Shielding of device by substrate --- p.67 / Chapter 5.3.2 --- Floor Planning --- p.68 / Chapter 5.4 --- Layout of Power Rail --- p.69 / Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70 / Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74 / Chapter 5.6.1 --- Proposed Architecture --- p.75 / Chapter 5.6.2 --- Traditional Architecture --- p.77 / Chapter 5.7 --- Summary --- p.79 / Chapter Chapter 6 --- Measurement Results --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Considerations of PCB Design --- p.82 / Chapter 6.3 --- Measurement Setup --- p.83 / Chapter 6.4 --- Measurement Results --- p.85 / Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85 / Chapter 6.5 --- Summary --- p.92 / Chapter Chapter 7 --- Conclusion --- p.95 / Chapter 7.1 --- Conclusion --- p.95 / Chapter 7.2 --- Future Works --- p.96 / References --- p.97 / Appendix --- p.100 / Chapter A.1 --- Publications --- p.100 / Chapter A.2 --- Schematic of proposed front end --- p.101 / Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102 / Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103 / Chapter A.5 --- Schematic of biasing circuit --- p.104 / Chapter A.6 --- Schematic of preamplifier in comparator --- p.105 / Chapter A.7 --- Schematic of latched part in comparator --- p.106 / Chapter A.8 --- Schematic of the clock generator --- p.107

Finally, a four-channel SIMO converter with direct combination but optimal switching sequence for arbitrary converter sequence and converter type is presented. The theoretical optimal 1st-order inductor waveform from this proposed control algorithm is introduced. FCL is involved in this design to realize the algorithm. Moreover, a current-modulated ramp signal, which couples to different controllers, is included to compensate the original deep correlated power stages. By using all of the proposed techniques, Measurement results show that both conduction loss and dynamic loss can be suppressed because of the optimized switching sequence. The load transient response time is around 100mus. The peak efficiency is 89% with a 2.5-V power supply. A maximum output power of 1.66W can be achieved. / Firstly, a pseudo-PWM hysteresis voltage-mode buck converter is proposed. It achieves fast transient speed by the hysteresis control, estimable switching spectrum with a locking frequency and fast mode switching between PWM and PFM depending on the loading change. Measurement results show that the recovery time under the load transient is around 5mus, which is 5 times of the switching period. The boundary of the recovery time is defined by the value of the off-chip inductor. / Switching-mode power converter (SMPC) is an important circuit block in electronic systems. In the modem SMPC system, constant frequency voltage or current-mode control technique is commonly used. However, some limitations are raised due to some preliminary settings in the design. In this thesis, the switching frequency or period is no longer a constant but a design variable. Then, an additional frequency-control loop (FCL) is introduced in order to obtain a fixed frequency operation in the steady state. Three individual designs implemented with different types of FCL are proposed to verify the concept. / Then, a four-channel SIMO converter based on FCL is developed, together with auto-phase allocation technique. This circuit not only solves the problem of imbalance loading of different channels, but it also keeps the idle period of the inductor sufficient short in the full operation region. By combining with all channel controllers, FCL makes fast load transient response without degrading the power efficiency. Moreover, linear auto converter-type adaption technique is also used, which makes the converter surviving from a wide input range and output range. Measurement results show that the proposed converter can achieve a peak efficiency of 89%, a total output power of 1.46W, a load transient response time of less than 70muS, and an idle inductor period of <10%. / Zheng, Yanqi. / Adviser: Leung Ka Nang. / Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Energy security concerns and the impact of traditional sources of power generation on the climate have prompted a rise in renewable energy expansion around the world. Power transmission from remote generation sites to consumers over long distance is most efficient using High-Voltage Direct Current (HVDC) transmission lines. Consequently, HVDC and the integration of renewable resources are considered as key perspectives in the improvement of sustainable energy systems capable of secure and stable electric power supply. With the intention of huge energy demand in the future, the multi-terminal DC grid concept is proposed based on various converter topologies like Line Commutated Converter (LCC), Voltage Sourced Converter (VSC), and Modular Multilevel Converter (MMC) HVDC technologies. These converters play a vital role in integrating remotely-located renewable generation and reinforcing existing power systems. The MMC has become increasingly popular in HVDC transmission compared to conventional line commutated converters, two-level and multilevel voltage source converters. Low generation of harmonics, a low switching frequency of semiconductors, sine formed AC voltages and currents, black start capability and higher overall efficiency are a few of the unique features of MMC. The MMC is characterised by a modular arm structure, formed by a cascade connection of a vast number of simple cells with floating DC capacitors. These cells are called Sub-Modules (SMs) and can be easily assembled into a converter for high voltage power conversion systems. Compared with traditional VSCs, the analytical modelling of MMC is more challenging. This is because of technical issues such as higher order system, the discontinuous and non-linear nature of signal transfer through converters, the complexity of the interaction equations between the AC and DC variables, and harmonic frequency conversion through AC side and DC side of the converter. This work intends to resolve these challenges by developing a detailed non-linear model using fundamental switching Selective Harmonic Elimination (SHE) modulation technique, an average MMC model in DQ0 frame and an analytical dynamic MMC model, which can be suitable for small-signal stability studies, and control design. Firstly, the detailed model of MMC using fundamental switching SHE modulation scheme has been developed using PSCAD/EMTDC (Power systems computer aided design Electromagnetic transients for DC) software. The basic terms and equations of the MMC have been presented along control loops. The significance of the switching frequency on the performance of the MMC has been studied as well as the relation between the switching frequency, the Total Harmonic Distortion (THD) and the number of output voltage levels. Detailed representation of MMC systems in PSCAD/EMTDC programs incorporates the modelling of Insulated-Gate Bipolar Transistor (IGBT) valves and should typically utilise small integration time-steps to represent fast switching events precisely. Computational burden introduced by such detailed models make the study of steady-state and transient events more complex, highlighting the need to implement more efficient models that provide comparative behaviour and dynamic response. Secondly, average DQ0 models has been implemented to accurately replicate the steady-state, dynamic and transient behaviour of MMC in PSCAD/EMTDC programs. These simplified models represent the average response of switching devices and converters by using averaging techniques involving controlled sources and switching functions. Developing the MMC average model in DQ0 frame was a challenging task because of the multiplication terms in the MMC average model in ABC frame. The proposed approach to overcome this challenge is considering generic form for the product variables and multiplying them in ABC frame and then transferring only the DC and fundamental frequency components of the results to DQ0 frame. The comparisons between detailed model and the average model validated the effectiveness of the average model in representing the dynamics of MMC. It is at least one hundred times faster than the detailed model for the same simulation time step. Finally, a dynamic analytical MMC model and associated controls have been proposed. To enable the model application to a broad range of system configurations and various dynamic studies, the model is built on a modular modelling approach using four sub-systems; an AC system, Phase Locked Loop (PLL) system, MMC system and a DC arrangement. The developed MMC system model has been linearized and implemented in state-space form. To select the best open-loop controller gains, eigenvalue analysis is performed for each particular test system. The rationality and correctness of the proposed model are verified against non-linear PSCAD/EMTDC simulations, and good accuracy is obtained in the time domain analysis. Further, the model is also verified in the frequency domain, and it is concluded that the developed model can be employed for dynamic analysis below 300 Hz.

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. / Includes bibliographical references (p. 85-86). / The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation. / by Yanlok Charlotte Lau. / M.Eng.