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Incorporating the effect of delay variability in path based delay testingTayade, Rajeshwary G. 19 October 2009 (has links)
Delay variability poses a formidable challenge in both design and test of nanometer
circuits. While process parameter variability is increasing with technology scaling, as circuits
are becoming more complex, the dynamic or vector dependent variability is also increasing
steadily. In this research, we develop solutions to incorporate the effect of delay variability
in delay testing. We focus on two different applications of delay testing.
In the first case, delay testing is used for testing the timing performance of a circuit
using path based fault models. We show that if dynamic delay variability is not accounted for
during the path selection phase, then it can result in targeting a wrong set of paths for test.
We have developed efficient techniques to model the effect of two different dynamic effects
namely multiple-input switching noise and coupling noise. The basic strategy to incorporate
the effect of dynamic delay variability is to estimate the maximum vector delay of a path
without being too pessimistic.
In the second case, the objective was to increase the defect coverage of reliability
defects in the presence of process variations. Such defects cause very small delay changes and hence can easily escape regular tests. We develop a circuit that facilitates accurate
control over the capture edge and thus enable faster than at-speed testing. We further
develop an efficient path selection algorithm that can select a path that detects the smallest
detectable defect at any node in the presence of process variations. / text
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Modeling and Analysis of High-Frequency Microprocessor Clocking NetworksSaint-Laurent, Martin 19 July 2005 (has links)
Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems.
The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.
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