Copper interconnects and low k dielectrics have been introduced in advanced IC technology to reduce the interconnect resistance, improve the resistance to electromigration and reduce RC delay and cross talk effects. The introduction of new materials in integrated circuits makes the root cause determination and correction action implementation more challenging. Moreover, the complexity of package structure generates additional impact on degrading the yield of assembly processing manufacture. This main purpose of this study is to investigate the influence of introducing Cu-/Low K wafer phase on actual manufacturing situation. Issues related to the failures of assembly process were analyzed for determining the root cause, in which such as die chipping issue during die sawing process, bond pad peeling/crater issues during wire bonding process and die crack / delamination issues after pre-condition and reliability test. The DOE/JMP methodology was used to achieve the optimium assembly processing condition so as to improve the quality of products, and then the mass production with stable yield could be realized.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text

The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.

This dissertation constitutes two major sections. In the first major section, a kinetic analysis was established to investigate the electromigration (EM), enhanced intermetallic compound (IMC) growth and void formation for Sn-based Pb-free solder joints to Cu under bump metallization (UBM). The model takes into account the interfacial intermetallic reaction, Cu-Sn interdiffusion, and current stressing. A new approach was developed to derive atomic diffusivities and effective charge numbers based on Simulated Annealing (SA) in conjunction with the kinetic model. The finite difference (FD) kinetic model based on this approach accurately predicted the intermetallic compound growth when compared to empirical observation. The ultimate electromigration failure of the solder joints was caused by extensive void formation at the intermetallic interface. The void formation mechanism was analyzed by modeling the vacancy transport under electromigration. The effects of current density and Cu diffusivity in Sn solder were also investigated with the kinetic model. The second major section describes the integration of Step and Flash Imprint Lithography (S-FIL®) into an industry standard Cu/low-k dual damascene process. The yield on a Back End Of the Line (BEOL) test vehicle that contains standard test structures such as via chains with 120 nm vias was established by electrical tests. S-FIL shows promise as a cost effective solution to patterning sub 45 nm features and is capable of simultaneously patterning two levels of interconnect structures, which provides a low cost BEOL process. The critical processing step in the integration is the reactive ion etching (RIE) process that transfers the multilevel patterns to the inter-level dielectrics (ILD). An in-situ, multistep etch process was developed that gives excellent pattern structures in two industry standard Chemical Vapor Deposited (CVD) low-k dielectrics. The etch process showed excellent pattern fidelity and a wide process window. Electrical testing was conducted on the test vehicle to show that this process renders high yield and consistent via resistance. Discussions of the failure behaviors that are characteristic to the use of S-FIL are provided. / text