Bus interfaces keep getting faster and thus requiring designers to build custom physical fabrics that are able to delay clock and(or) data, on their transmitter and receivers, in order to properly receive and send data with enough setup and hold times. Delay locked loops (DLLs) have become fundamental building blocks that address such problems. Not only are they present in physical layers in integrated circuits but they also solve the problem of VLSI systems that suffer from clock skew and jitter. This report focuses on the implementation of a standard DLL and three different voltage controlled delay topologies. The different topologies are designed and compared for metrics such as linearity, delay range, and sensitivity to power supply. / text

In this work a low voltage and highly linear current-mode current to delay (CTD) converter is presented. The proposed current to delay converter has the improved linearity of about 23.5% when compared with a conventional–delay inverter over the input dynamic current range of 50µA. When used as front-end block in current-mode delay-mode analog to digital converter an 11-bit resolution is obtained. The design is implemented in TSMC 90 nm CMOS technology. Monte Carlo analysis and process corner analysis is performed on the proposed circuit to analyze the amount of mismatch that will degrade the performance of the circuit in a system level. A Process, Voltage, and Temperature (PVT) variation insensitive circuit is used to bias the designed CTD converter to obtain 57% reduction of variation when compared with the simple current mode biasing technique.

Les systèmes de communication sans fil modernes exigent haute performance analogique Convertisseurs-numériques (CAN) avec l'augmentation de la bande passante et la résolution.Aujourd'hui, il y a un besoin croissant de faible puissance et de récepteurs RF multi-fonctionnels, puisque le marché s' attend à des capacités de réception complexes avec des appareils de faible puissance qui fonctionnent sur batteries portables de puissance limitée.Pour cette raison la tendance actuelle est de diminuer la partie analogique des récepteurs, tout en augmentant les tâches effectuées par la partie numérique.Par conséquent, cela demande des CAN à large bande, haute résolution et faible consommation.Dans cette recherche, on étudie plusieurs CAN à base de VCO.On montre la conception, la réalisation dans le process CMOS 65nm et les mesures de deux types de CAN à base VCO, le premier est basé sur le principe de la conversion tension-fréquence tandis que le second utilise le principe de la conversion tension-phase.Le CAN tension fréquence est un CAN de 4-bit programmable avec une fréquence d’échantillonnage qui va de 220MHz jusqu’à 1500MHz. le rapport signal dur bruit mesuré est de 40.5dB dans une bande de 30MHz avec une consommation de 0.5mW.Le CAN tension phase est un CAN de 4-bit programmable avec une fréquence d’échantillonnage qui va de 300MHz jusqu'a 1440MHz. le rapport signal dur bruit mesuré est de 48dB dans une bande de 30MHz avec une consommation de 1mW. On présente ensuite une méthode de conception systématique de conception des CAN SigmaDelta de grand ordre avec des quantificateurs à base VCO.Pour valider la méthode de conception, un CAN SigmaDelta avec un quantificateur tension-fréquence est conçu en 65nm. Le rapport signal sur bruit mesuré est de 62dB dans une bande de 28MHz et une consommation de 30mW.On propose ensuite l'utilisation des quantificateurs à base VCO dans les modulateurs SigmaDelta en quadrature. Pour cela, une méthode de conception systématique et présentée. Un CAN sigmadelta en quadrature de 4ème ordre avec des quantificateurs tension fréquence est conçu en 65nm. Les mesures de ce circuit sont encore encours. Les simulations post-layout montrent un rappost signal sur bruit de 75dB dans une bande de 40MHz et une consommation de 60mW. / Today's wireless communication systems are requiring high performance Converters analog-digital (ADC) with increasing demand on bandwidth and resolution.There is a growing need for low-power and multi-functional RF receivers , since the market is expecting complex receiving capacities with low power battery operated devices.For this reason the current trend is to decrease the analogue part of the receivers, while increasing the tasks performed by the digital part.Therefore, this imposes stringent requirements on the ADC such as wideband operation, high resolution and low power consumption.In this dissertation, we studied and realized several types of VCO-based ADCs.We show the design, implementation and the measurements of two types of VCO-based ADCs in 65nm CMOS process. The first is using the voltage to frequency conversion technique while the second uses the principle of voltage to phase conversion.The voltage to frequency converter is a 4-bit ADC with a programmable sampling frequency that goes from 220MHz up to 1500MHz.The measured Signal-to-noise-and-distortion-ratio (SNDR) is of 40.5dB in a band of 30MHz with a power consumption of 0.5mW.The voltage phase converter is a 4-bit ADC with a programmable sampling frequency that goes from 300MHz up to 1440MHz.The measured SNDR is 48dB in a band of 30MHz with a consumption of 1mW.We then present a systematic design method of high order SigmaDelta ADCs with VCO-based quantizers.To validate the design method, a SigmaDelta ADC with a 4-bit voltage-frequency is designed in 65nm. The measured SNDR is 62dB in a band of 28MHz and a power consumption of 30mw.We propose the use of VCO-based quantizers in quadrature SigmaDelta modulators. A systematic design method is presented for the quadrature VCO-based Sigmadelta modulators.A 4th order quadrature sigmadelta with 4-bit voltage to frequency quantizers is designed in 65nm. The measurements of this circuit are currently in progress. In post layout simulations, the quadrature modulator achieves 75dB in a band of 40MHz and a power consumption of 60mW.

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

This project focus to desing an on-chip oscillator in function as a clock generator. Frequency stability of the oscillator is affected by supply voltage, temperature and process variations. The aim is to propose a clock generator with sufficient frequency stability, low power consumption and a small chip area. This work deals with the types of oscillators and their basic building blocks suitable for our application. It also deals with the study and design options of temperature and process compensation circuit generating the current control, which provides the frequency stabilization of the output signal.

A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.