Aside from performance, energy efficiency is an increasing challenge in database systems. To tackle both aspects in an integrated fashion, we pursue a hardware/software co-design approach. To fulfill the energy requirement from the hardware perspective, we utilize a low-energy processor design offering the possibility to us to place hundreds to millions of chips on a single board without any thermal restrictions. Furthermore, we address the performance requirement by the development of several database-specific instruction set extensions to customize each core, whereas each core does not have all extensions. Therefore, our hardware foundation is a low-energy processor consisting of a high number of heterogeneous cores. In this paper, we introduce our hardware setup on a system level and present several challenges for query processing. Based on these challenges, we describe two implementation concepts and a comparison between these concepts. Finally, we conclude the paper with some lessons learned and an outlook on our upcoming research directions.

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En av hörnstenarna inom Industri 4.0 och den moderna anslutningen på fabriksgolvet är användningen av standardiserade kommunikationsprotokoll. Med utvecklingen av kommunikation idag och dess användning i industrier blir behovet av att överföra information snabbt mer akut. I denna avhandling har etablerade IIoT-kommunikationsprotokoll utvärderats för deras prestanda för dataöverföringshastighet mellan system. De analyserade kommunikationsprotokollen är OPC-UA, MQTT, AMQP och ROS. Testmiljön för att utvärdera protokollen består av två datorer som är anslutna via en switch. Testerna består av att skicka tre typer av data, en bild i form av en bytearray, en JSON-fil och heltal. Resultaten av testet kommer att jämföras genom att se hur snabbt protokollen kan skicka dessa typer av data samtidigt. Resultaten kommer sedan att analyseras för att föreslå ett lämpligt protokoll för ett distributionssystem som skickar dessa typer av data. / One of the cornerstones of Industry 4.0 and the state-of-the-art industrial shop floor connectivity is the use of standardized communication protocols. With the development of communications today and its use in industries, the need to transfer information quickly becomes more urgent. In this thesis common IIoT communication protocols have been evaluated for their performance for data transfer rate between systems. The communication protocols that are analyzed are OPC-UA, MQTT, AMQP, and ROS. The test bench for evaluating the protocols is made up of two computers connected by a switch. The tests consist of sending three types of data, an image in the form of a bytearray, a JSON file and integers. The results of the test will be compared by seeing how fast the protocols can send these types of data concurrently. The results will then be analyzed to propose a suitable protocol for a distributed system sending these types of data.

Dans la majorité des secteurs industriels, les coûts de maintenance des systèmes de production représentent une partie non négligeable de l’ensemble de ces coûts. Pour améliorer les performances et la fiabilité des systèmes, différentes stratégies de maintenance sont utilisées. L’objectif est d’être capable de détecter toutes défaillances potentielles susceptibles d’affecter la production. L’analyse vibratoire est aujourd’hui un des outils les plus performants en termes de détection et de suivi de ces défaillances. Cependant, l’application de cette technique reste difficile dans le cas de machines fonctionnant avec des vitesses de rotation faibles et variables. Dans la présente thèse, nous proposons une technique alternative à l’analyse vibratoire pour surveiller l’état de fonctionnement de ces machines. Nous nous intéresserons plus particulièrement au suivi des roulements. Cette technique alternative se base sur l’analyse des variations de la vitesse angulaire instantanée qui sont générées par un défaut de roulement. Cette technique sera testée sur un banc d’essai et comparée avec d’autres techniques telles que l’analyse des signaux vibratoires et ultrasonores pour différentes conditions de chargement et pour différents types de défauts de roulement. Cette étude montre une grande efficacité de cette méthode dans le cas de très basses vitesses de rotation, constantes ou variables. L’ensemble de cette méthodologie a ensuite été implémentée sur un four de diffusion d’une unité de production sucrière. Les mesures réalisées montrent que cette technique est une technique prometteuse pour le suivi de systèmes fonctionnant avec des vitesses de rotation faibles et variables. / In the majority of industrial sectors, production systems’ maintenance costs represent an important part of the whole process’s cost. In order to improve systems’ reliability and performance, different maintenance strategies are used. The goal is to be able to detect all potential malfunction that may affect the production. Nowadays, vibration analysis is one of the best tools in term of detection and defect monitoring. However, the application of these vibration based techniques remain difficult in the case of machines functioning at low speeds. In this thesis, we propose an alternative technique of vibration analysis for the surveillance of these machines that operate on very low speeds and variable speeds. We are specifically interested in bearings’ monitoring. This alternative technique is based on instantaneous angular speed’s variations analysis that are induced by a bearing defect. This technique is tested on a test bench and compared with other techniques such as vibration and ultrasound analysis for different loading conditions and for different bearing fault types. This study shows a high efficiency of this method in the case of very low speeds, constant and variable. This methodology has then been implemented on sugar diffusion oven in a sugar production factory. The measurements shows that this technique is a promising technique for machines’ surveillance in very low and variable speeds working conditions.

SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a testplan that identifies the conditions to be verified, (ii) a testcase that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design. Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and reused. In this work we present a methodology to synthesize testcases from reusable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of testcases, (ii) identifying code segments of testcases that can be reused from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the testcase, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize testcases. We discuss two specific classes of testcases. These are testcases for verifying the memory modules and the testcases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype testcase generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of testcases automatically that are correct by construction and (ii) reuse of the testcase code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.

This thesis deals with operation of the Jasenie hydroelectric power plant, which supplies electricity to Železiarne Podbrezová Inc. This thesis describes actual operation, devices and equipment in all substations. The second chapter briefly describes company’s history and activities of the company. The next chapter mentions an overview of the sources of own electricity production. The fourth chapter in detail deals with actual situation of the hydroelectric power plant operation, describes devices and equipment in all substations. It also outlines what measures should be taken to increase the reliability of electricity supply. Next part deals with replacing insulators on the 22 kV line. Sixth chapter is focused on protection this line by multifunctional protection relay and data transfer from HC Jasenie to the building of power engineering. In the next step is designed a backup transformer with bus control for thermal and dynamic effects of the short-circuit current. The last chapter is focused on surge protection in HC Jasenie as well as in the area of Stary závod substation. The results and benefits of this work are summarized in the conclusion. The attachment contains schemes of substations and overall overview scheme, which are used for better understanding of this problem.

This term paper deals with subject of wireless communication of city rail transport cars. In this paper are described individual modules for transmission and receiving of data containing communication between city rail transport cars and measures of siding switches. Then there are discussed possibilities of design of system for testing functionality of transmitting and receiving modules and the system is consequently designed. There are also described communication principles and protocol used for wireless communication and MODBUS protocol used for communication over RS-485 serial line. In the end was the system manufactured, completed and equipped with necessary software.

This work deals with the design and implementation of high-speed communication interfaces into FPGA chip and their utilizing for image transmission and processing. In the implementation part has been created PCI Express endpoint device, which provides data transfers between the FPGA chip and computer RAM memory. As a source of image data for further processing was connected the Unicam M621 camera throught the Ethernet interface to FPGA chip. The project was implemented on the Xilinx SP605 development board. Using both of the the interfaces were demonstrated on the application of edge detection using Sobel operator. The PCI Express endpoint device driver for the Linux operating system and a simple application interface in C language was also created within this project.

The interlinking of enriched BIM data to Building Energy Performance Simulation (BEPS) models facilitates the data flow throughout the building life cycle. This seamless data transfer from BIM to BEPS models increases design efficiency. To investigate the interoperability between these models, this paper analyses different data transfer methodologies along with input data requirements for the simulation process. Based on the analysed knowledge, a methodology is adopted and demonstrated to identify the quality of the data transfer process. Furthermore, discussions are provided on identified efficiency gaps and future work.:Abstract Introduction and background Methodology Methodology demonstration Creation and export of BIM data Verification of OpenBIM meta-data BEPS model generation and validation Import statics Model Geometry and Orientation Construction details Thermal Profile Results and discussion Summary and future work References

<div>Field Programmable Gate Arrays(FPGAs) were invented in the 1980s. Since then the use of FPGAs in many fields has been growing rapidly. Due to the inherent reconfiguration and relatively low development cost FPGA technology has become one of the important components in data processing and communication system.</div><div>The recent development of computing technology affects not only the software but also requires integrating and utilizing a custom logic design on a dedicated hardware platform.</div><div>In this context,this research work analyzes and compares on-chip interfaces of HW/SW communication in the Zynq-7000 all programmable SoC based platform. Several experiments were carried out to evaluate the performance of data communication between the processing system and programmable logic through general purpose(GP), high performance ports (HP) and accelerator coherency port (ACP). The results identified the most effective interfaces for transferring data from the PL to PS and store the data to DRAM memory.</div><div>One conclusion of this work is that, the selection of suitable ports depends on application requirements. For low-bandwidth application GP port is appropriate. For high-speed applications, the high performance port(HP) and Accelerator Coherency Port (ACP) are suitable and works better.The results of this thesis are useful in high performance embedded system design.<br></div><div><br></div><div><br></div>