Cette thèse de doctorat porte sur les fluctuations temporelles du flux lumineux des lampes LED, ce phénomène portant le nom de papilottement (flicker). Le papillotement est habituellement considéré comme une perturbation en raison de son impact négatif sur la santé. Pour les systèmes d'éclairage à base de diodes électroluminescentes (LED), sa définition vient d'être formalisée dans la norme IEEE 1789:2015 et a été décrite pour les appareils alimentés en courant alternatif (CA). Ce papillotement alternatif résulte des interactions entre l'impédance du réseau, l'onde de tension, les courants harmoniques et le convertisseur de courant alternatif en courant continu (CA - CC). L'alimentation en courant continu est généralement obtenue via des convertisseurs à découpage. Par conséquent, les mêmes facteurs perturbateurs sont également présents sur les réseaux à courant continu. Cette thèse résume les diférences entre les propriétés caractéristiques du papillotement sous alimentation en CA et en CC. Il a été montré dans la littérature et aussi dans cette thèse qu'avec les LED, le facteur clé qui affecte le papillotement réside dans la conception du driver de LED - une partie indispensable des systèmes d'éclairage à LED. Cette thèse décrit une méthodologie d'évaluation de la sensibilité au papillotement des lampes LED sous alimentation en CC et analyse la façon dont cette sensibilité se modifie lorsque les drivers de LED sont simplifiés et adaptés à des alimentations CC. La thèse présente un ensemble d'expériences de mesure visant à déterminer la réaction typique du papillotement des lampes LED à la fois sous alimentation CA et CC. D'autres expériences ont été efectuées pour révéler l'impact de l'adaptation du driver à l'alimentation CC (en enlevant le pont redresseur à diodes). On constate que certaines lampes présentent une meilleure résistance au papillotement, tandis que d'autres lampes présentent une moindre résistance. Ces expériences sont accompagnées de simulations de drivers pour les lampes LED visant à reproduire et à expliquer les résultats des mesures. La thèse décrit en outre une expérience de mesure visant à montrer la sévérité typique de la variation de tension dans un réseau CC à basse tension couplé au CA domestique et son impact sur le papillotement. On conclut qu'un tel système est suisamment robuste pour filtrer les perturbations provenant du CA, mais une interaction indésirable entre la lampe et l'alimentation peut se produire. / This dissertation thesis is concerned with temporal fluctuations of the luminous flux of LED lamps, a phenomenon referred to as flicker. Flicker is usually regarded as a disturbance due to its negative impact on human health. For lighting systems based on light emitting diodes (LED), its definition has recently been formalised in norm IEEE 1789-2015 and has been documented on devices supplied with AC voltage. AC flicker results from interactions between network impedance, voltage and current harmonics, and the AC to DC converter. DC supplies are generally obtained by switching converters. Consequently, the same perturbing factors are present on DC networks. The thesis summarises the differences between the characteristic properties of flicker under AC and DC supplies. It has been shown in the literature and also in this thesis that the key factor affecting flicker with LEDs is the design of the LED driver-a necessary part of the LED lighting systems. This thesis describes a methodology for the evaluation of the flicker sensitivity of DC supplied LED lamps and analyses how the sensitivity changes when the LED drivers are simplified and accustomed to DC supply. The thesis presents a set of measurement experiments aimed to determine the typical flicker response of LED lamps both under AC and DC supply. Further experiments were performed to reveal the impact of accustomising the driver to the DC supply (removing the diode rectifier). It was found that some lamps show better flicker immunity while other lamps show worse flicker immunity. These experiments are accompanied by LED driver simulations aiming to reproduce and explain the measurement results. The thesis further describes a measurement experiment aimed to show the typical severity of the voltage fluctuation in a low voltage DC network coupled to AC mains and its impact on the flicker. It is concluded that such a system is robust enough to filter out any perturbations coming from the AC supply, but an undesired interaction between the lamp and the supply may occur.

For low and medium power applications, conventional two-level inverters are widely used in industrial applications including electric vehicle drives, traction drives, distributed generation, power management and grid connected renewable energy systems. To filter out the harmonic currents from the load, passive line filters are used. These filters are designed to pass the fundamental phase current and suppress higher harmonic currents, making the filters bulky. To get a nearly sinusoidal current waveform, these two level inverters are switched at high frequency to shift the harmonic components in the phase current to high frequencies to reduce size and cost of the filter. But higher switching frequencies have some drawbacks like large dV /dt stresses on the motor terminals and switching devices, leading to electro-magnetic interference (EMI) problems and higher switching losses. For full DC bus utilization to enhance the power output from the two level inverter, the inverter has to operate in overmodulation region up to the six-step operation. Considerable fifth and seventh order (6n ± 1, n = odd) harmonics are produced when the inverter operates in overmodulation region. These include some low order harmonics like fifth and seventh, which are currently suppressed by using bulky passive line filters. Different high frequency modulation schemes are uniquely used in overmodulation region to suppress these harmonics. Another well accepted method of harmonic suppression is the selective harmonic elimination (SHE) techniques. SHE introduces notches at specific angles in a fundamental period of the inverter pole voltage to eliminate a particular harmonic component from the pole voltage. But, SHE involves extensive offline computation and requirement for higher memory for implementation of huge lookup tables. dodecagonal voltage space vectors have been reported in literature. Dodecagonal voltage space vector structures inherently eliminate fifth and seventh order (6n ± 1, n = odd) harmonics from the phase voltage. However, these require multiple isolated and unequal DC supplies (like VDC and 0.366VDC ). Generating DC voltage supplies at particular ratio to the main DC supply, requires additional circuitry. This increases the size of the converter and four quadrant back to back operation is not possible for the converter. To overcome the problems mentioned above, a novel switched capacitive filtering technique is proposed in this work for low and medium power drives applications. The filtering is done by an inverter fed by capacitor. A novel method to ensure zero power contribution by an inverter is shown, enabling the inverter to be fed by a capacitor. Thus, the capacitor fed inverter is shown to operate as a switched capacitive filter, which generates harmonic voltages that gets eliminated from the phase voltage of conventional two level inverters. With the proposed switched capacitive filtering technique, the following benefits are achieved. • Fifth and seventh order (6n ± 1, n = odd) harmonics are eliminated from the phase voltage, for the full modulation range of the two level inverters even while operating in overmodulation region and six-step mode. Thus, bulky passive line filters are avoided. • Since, the capacitive filter does not contribute any active power to the load, single DC supply operation is possible. Hence, four quadrant back to back operations is possible with the proposed filtering technique. • Dodecagonal voltage space vector structures are realized using single DC supply for the first time. • Modulation techniques for different power circuit topologies have been proposed which inherently controls the capacitor voltage at specific voltage levels for the full modulation range of the inverter including six-step operation. Hence, no additional pre-charging circuitry is required. • High frequency switching is shifted to the capacitive filter which is at a low voltage compared to the DC supply fed power contributing inverter. Thus, the main inverter need not be switched at high switching frequency for harmonic suppression. This reduces the switching loss as compared to conventional inverters, to achieve harmonic suppression of comparable order. • Reduced voltage stress on the switches of the switched capacitive filter. Hence, low voltage devices can be used to implement the switched capacitive filter, reducing the cost and size drastically as compared to conventional passive line filters. The proposed switched capacitive filtering scheme has been realized for open-end winding induction motor drive and three phase star connected three terminal induction motor drive where conventional two level inverter is used as the power contributing inverter. Additionally, extension of the capacitive filtering scheme to multilevel inverter fed drives is also shown, where the main power contributing inverter is a three level flying capacitor (FC) inverter. The power circuit implementations are briefly described as following. (i) In open-end winding three phase induction motors, the two terminals of each of the three phase windings are accessed. The main DC bus connected two level inverter feeds power from one end of the motor terminals. A capacitor fed two level inverter eliminates the fifth and seventh order harmonics from the other end for the full modulation range including overmodulation and six-step operation of DC bus fed inverter. The voltage space vectors from both the inverters connected at opposite ends of the motor forms dodecagonal voltage space vectors. An uniform pulse width modulation (PWM), for the full modulation range is proposed which switches from the dodecagonal voltage space vectors while inherently maintaining the capacitor voltage at 0.289VDC . (ii) In conventional star connection of three phase induction motors, all three terminals of the three phase windings are shorted from one end, leaving access to just three terminals. Such three terminal induction motor fed to conventional two level inverter is commonly used in many drives applications. Capacitor fed H-bridges are cascaded to such two-level inverters, to eliminate the fifth and seventh order harmonics from the phase voltage for the full modulation range including overmodulation and six-step operation of DC fed inverter. The voltage space vectors from capacitor fed H-bridges get added to the voltage space vectors from the two level inverter to form dodecagonal voltage space vectors. A PWM technique for the full modulation range is proposed to switch from the dodecagonal voltage space vector while inherently maintaining the three H-bridge connected capacitor voltages at 0.1445VDC . (iii) Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single DC supply. A DC supply fed three level flying capacitor (FC) inverter feeds active power to one end of the induction motor winding terminals and H-bridge connected capacitors eliminate fifth and seventh order harmonics from the other end of the motor winding terminals. The voltage space vectors from the three level FC inverter and the H-bridge inverter forms a three level dodecagonal voltage space vectors with symmetric triangular sectors. A PWM technique is developed to switch the three level dodecagonal space vectors and simultaneously control the H-bridge connected capacitors at 0.1445VDC . The fifth and seventh order harmonics are eliminated for the full modulation range of the three level FC inverter, including the extreme six-step operation. Additionally, the proposed inverter has also been shown to operate for rotor field oriented vector control of the open-end winding induction motor drive. For all the power circuit implementation of the switched capacitive filter, an increase of 7.8% in the linear modulation range (up to 48.8Hz) is achieved, implying better DC bus utilization as compared to conventional inverter topologies switching from hexagonal voltage space vectors. With advantages like fifth and seventh order (6n ± 1, n = odd) harmonic elimination throughout the modulation range, reduced dv/dt stress, lower switching frequency in high voltage devices, single DC supply requirement, dodecagonal voltage space vector switching, PWM technique with inherent capacitor balancing, increased linear modulation range and reduced voltage stress on high frequency switches, the proposed switched capacitive filtering scheme is well suited for low and medium power drives application with requirements for high dynamic performance and precise speed control.