Submitted by PPG Ci?ncia da Computa??o (ppgcc@pucrs.br) on 2018-04-03T14:30:24Z No. of bitstreams: 1 MARCELO_MELO_LINCK_DIS.pdf: 4153250 bytes, checksum: 821a8f1e65f49c1b24a0b69b4f6e7f94 (MD5) / Approved for entry into archive by Tatiana Lopes (tatiana.lopes@pucrs.br) on 2018-04-12T21:09:45Z (GMT) No. of bitstreams: 1 MARCELO_MELO_LINCK_DIS.pdf: 4153250 bytes, checksum: 821a8f1e65f49c1b24a0b69b4f6e7f94 (MD5) / Made available in DSpace on 2018-04-12T21:23:08Z (GMT). No. of bitstreams: 1 MARCELO_MELO_LINCK_DIS.pdf: 4153250 bytes, checksum: 821a8f1e65f49c1b24a0b69b4f6e7f94 (MD5) Previous issue date: 2018-03-22 / Acessos simult?neos gerados por m?ltiplos clientes para um ?nico dispositivo de mem?ria em um Sistema-em-Chip (SoC) imp?e desafios que requerem aten??o extra devido ao gargalo gerado na performance. Considerando estes clientes como processadores, este problema torna-se mais evidente, pois a taxa de crescimento de velocidade para processadores excede a de dispositivos de mem?ria, criando uma lacuna de desempenho. Neste cen?rio, estrat?gias de controle de mem?ria s?o necess?rias para aumentar o desempenho do sistema. Estudos provam que a comunica??o com a mem?ria ? a maior causa de atrasos durante a execu??o de programas em processadores. Portanto, a maior contribui??o deste trabalho ? a implementa??o de uma arquitetura de controlador de mem?ria composta por dois n?veis: prioridade e mem?ria. O n?vel de prioridade ? respons?vel por interagir com os clientes e escalonar requisi??es de mem?ria de acordo com um algoritmo de prioridade fixa. O n?vel de mem?ria ? respons?vel por reordenar as requisi??es e garantir o isolamento de acesso ? mem?ria para clientes de alta prioridade. O principal objetivo deste trabalho ? apresentar um modelo que reduza as lat?ncias de acesso ? mem?ria para clientes de alta prioridade em um sistema altamente escal?vel. Os experimentos neste trabalho foram realizados atrav?s de uma simula??o comportamental da estrutura proposta utilizando um programa de simula??o. A an?lise dos resultados ? dividida em quatro partes: an?lise de lat?ncia, an?lise de row-hit, an?lise de tempo de execu??o e an?lise de escalabilidade. / Simultaneous accesses generated by memory clients in a System-on-Chip (SoC) to a single memory device impose challenges that require extra attention due to the performance bottleneck created. When considering these clients as processors, this issue becomes more evident, because the growth rate in speed for processors exceeds the same rate for memory devices, creating a performance gap. In this scenario, memory-controlling strategies are necessary to improve system performances. Studies have proven that the main cause of processor execution lagging is the memory communication. Therefore, the main contribution of this work is the implementation of a memory-controlling architecture composed of two levels: priority and memory. The priority level is responsible for interfacing with clients and scheduling memory requests according to a fixed-priority algorithm. The memory level is responsible for reordering requests and guaranteeing memory access isolation to high-priority clients. The main objective of this work is to provide latency reductions to high-priority clients in a scalable system. Experiments in this work have been conducted considering the behavioral simulation of the proposed architecture through a software simulator. The evaluation of the proposed work is divided into four parts: latency evaluation, row-hit evaluation, runtime evaluation and scalability evaluation.

Master of Science / We are in an ever-increasing demand for computing power to sustain our technological advancements. A significant driving factor of our progress is the size and speed of memory we possess. Modern computer architectures use DDR4-based DRAM (Dynamic Random Access Memory) to hold all the immediate information for processing needs. Each bit in a DRAM memory module is implemented with a tiny capacitor and a transistor. Since the capacitors are prone to charge leakage, each bit must be frequently rewritten with its old value. A dedicated memory controller handles the periodic refreshes. If the cells aren't refreshed, the bits lose their charge and lose the information stored by flipping to either 0 or 1 (depending upon the design). Due to manufacturing variations, every tiny capacitor fabricated will have different physical characteristics. Charge leakage depends upon capacitance and other such physical properties. Hence, no two DRAM modules can have the same properties and decay pattern and cannot be reproduced again accurately. This DRAM attribute can be considered a source of 'Physically Unclonable Functions' and is sought after in the Cryptography domain. This thesis aims to characterize the decay patterns of commercial DDR4 DRAM modules. I implemented a custom System On Chip on AMD/Xilinx's ZCU104 FPGA platform to interface different DDR4 modules with a primitive memory controller (without refreshes). Additionally, I introduced electric and magnetic fields close to the DRAM module to investigate their effects on the decay characteristics.

A significant portion of the memory in servers today is often unused. Our large-scale study of HPC systems finds that more than half of the total memory in active nodes running user jobs are unused for 88% of the time. Google and Azure Cloud studies also report unused memory accounts for 40% of the total memory in their servers, on average. Leaving so much memory unused is wasteful. To address this problem, we note that in the context of CPUs, Turbo Boost can turn off the unused cores to boost the performance of in-use cores. However, there is no equivalent technology in the context of memory; no matter how much memory is unused, the performance of in-use memory remains the same. This dissertation explores architectural techniques to utilize the unused memory to boost the performance of in-use memory and refer to them collectively as Memory Turbo Boost. This dissertation explores how to turbo boost memory performance through memory replication; specifically, it explores how to efficiently store the replicas in the unused memory and explores multiple architectural techniques to utilize the replicas to enhance memory system performance. Performance simulations show that Memory Turbo Boost can improve node-level performance by 18%, on average across a wide spectrum of workloads. Our system-wide simulations show applying Memory Turbo Boost to an HPC system provides 1.4x average speedup on job turnaround time. / Doctor of Philosophy / Today's servers often have a significant portion of their memory unused. Our large-scale study of HPC systems finds that more than half of the total memory of an HPC server is unused for most of the time; Google and Azure Cloud studies find that 40% of the total memory in their servers is often unused. Today's servers usually have 100s of GBs to TB memory; 40% unused memory means 10s-100s of GBs unused memory on the servers. Leaving so much memory unused is wasteful. To address this problem, I note that there are techniques to leverage unused hardware resources to improve the performance of in-use resources in other types of hardware. For example, CPU Turbo Boost can turn off the unused cores to boost the performance of in-use cores; modern SSDs can use the unused space to switch the Multi-Level Cell blocks to Single-Level Cell blocks to boost performance. However, there is no equivalent technology in the context of memory; no matter how much memory is unused, the performance of in-use memory remains the same. This dissertation explores techniques to utilize the unused memory to boost the performance of in-use memory and refer to them collectively as Memory Turbo Boost. Performance evaluations show that Memory Turbo Boost can provide up to 18% average performance improvement.