This thesis addresses the design and implementation of a dual-mode channel decoder for two advanced wireless communication systems. One of the targetsystems is the digital video broadcasting for hand-held terminals (DVB-H) , and the other one is Worldwide Interoperability for Microwave Access (WiMAX) system based on the recently approved IEEE 802.16e. Both standards promise to deliver high data bandwidth within very broad regions. The error control coding schemes of both standards are all built on the similar concatenated code, with the exception of the way of data interleaving. Therefore, the decoders for both standards can be highly integrated. To achieve the low-cost and low-power decoder, this thesis proposes several novel design ideas. First, a fast dynamic multiple path convergence mechanism is proposed for the design of Viterbi decoder module, which can determine the survivor path at earlier stage. Furthermore, a new modified forward path prediction method is also presented which can efficiently predict the possiblesurvivor path such that the number of memory operations during the trace-back canbe significantly reduced. The proposed methodology can reduce up to 50% to 80%of memory operations compared with the best prediction scheme in the literature at high signal-to-noise ration. Secondly, for the block deinterleaver adopted by IEEE 802.16. a new multi-bank architecture is proposed by properly splitting and allocating the input data to suitable bank. The proposed block deinterleaver can be highly integrated with the byte-level convolutional deinterleaver adopted by the DVB-H standard by realizing the multiply First-In-First-Out (FIFO) data branches as the circular buffer. The other salient feature of the proposed dual-mode decoder is that all the major data storage units can all be realized by single-port memory such that the overall cost can be highly reduced.

A circuit design of baseband transceiver for direct sequence ultra-wide band system is presented in this thesis. A low complexity Viterbi decoder is also proposed. This Viterbi decoder circuit is based on compare-select-add unit and trace-forward architecture. The decision bit operator is reduced to one adder and this can lower down the hardware complexity. Further, two trace-forward operators are used in the survivor management unit. Only two single port SRAM¡¦s with a length of T are applied for reducing the area of memory. The chip is implemented by TSMC standard 0.18-£gm 1P6M CMOS process with core area 1.061 ¡Ñ 1.069 mm2. The post-layout simulation with 1.8V supply at 25 shows that the proposed direct sequence ultra-wide band system of baseband transceiver chip can work above 141 MHz with 86.41 mW power dissipation.

In this work we propose two techniques for symmetric multiple description coding with reduced storage space decoder. The first technique is multiple description scalar quantizer with linear joint de-coders. We propose an optimal design algorithm similar to Vaishampayan's algo-rithm, to which we add an index assignment optimization step. We also solve an additional challenge in the decoder optimization, by proving that the problem is a convex quadratic optimization problem with a closed form solution (under some mild conditions). Our tests show that the new method has very good performance when the probability of description loss is sufficiently low. The other technique is an improvement to the traditional multiple description coding scheme based on uneven erasure protection. We evaluate the asymptotical performance of both schemes for a Gaussian memoryless source. The analysis reveals that the improvement reaches over 1 dB for up to ten descriptions and low probability of description loss. From our experiments we observe that the improved scheme is very competitive comparing to other multiple description techniques as well. / Thesis / Master of Applied Science (MASc)

No description available.

In this research, we integrate the voice commands technique into Google Map. It means that we can control part of the movements for Google Map search without using the mouse or keyboard but with voice. Our voice command system is built on the client side. The biggest different between our system and state-of-the-art real-time speech processing system is that all the computation about the speech process always work on the client side. For our corpus, we choose the Top100 scenic spots in Taiwan and some specific control commands as our training data. In the experiment of our research, we make use of the different ways to train the acoustic models and design dictionary and language models to estimate the efficiency on our system. Actual usage in the system, we can move the map center to the specific location sequentially by voice command operations for location, control and coordinate. we estimate the overall search process time on some specific locations by different users. It spends 20.8 seconds in average which spends most of time in recording stage.

Dans les télécommunications, le débit-fiabilité et la complexité de l’encodage et du décodage (opération à virgule flottante-flops) sont largement reconnus comme représentant des facteurs limitant interdépendants. Pour cette raison, tout tentative de réduire la complexité peut venir au prix d’une dégradation substantielle du taux d’erreurs. Cette thèse traite de l’établissement d’un compromis limite fondamental entre la fiabilité et la complexité dans des systèmes de communications « outage »-limités à entrées et sorties multiples (MIMO), et ses scénarios point-à-point, utilisateurs multiple, bidirectionnels, et aidés de feedback. Nous explorons un large sous-ensemble de la famille des méthodes d’encodage linéaire Lattice, et nous considérons deux familles principales de décodeurs : les décodeurs à maximum de vraisemblance (ML) et les décodeurs Lattice. L‘analyse algorithmique est concentrée sur l’implémentation de ces décodeurs ayant comme limitation une recherche bornée, ce qui inclue une large famille de sphère-décodeurs. En particulier, le travail présenté fournit une analyse à haut rapport Signal-à-Bruit (SNR) de la complexité minimum (flops ou taille de puce électronique) qui permet d’atteindre a) une certaine performance vis-à-vis du compromis diversité-gain de multiplexage et b) une différence tendant vers zéro avec le non-interrompu (optimale) ML décodeur, ou une différence tendant vers zéro comparé à l’implémentation exacte du décodeur (régularisé) Lattice. L’exposant de complexité obtenu décrit la vitesse asymptotique d’accroissement de la complexité, qui est exponentielle en terme du nombre de bits encodés. / In telecommunications, rate-reliability and encoding-decoding computational complexity (floating point operations - flops), are widely considered to be limiting and interrelated bottlenecks. For this reason, any attempt to significantly reduce complexity may be at the expense of a substantial degradation in error-performance. Establishing this intertwined relationship constitutes an important research topic of substantial practical interest. This dissertation deals with the question of establishing fundamental rate, reliability and complexity limits in general outage-limited multiple-input multiple-output (MIMO) communications, and its related point-to-point, multiuser, cooperative, two-directional, and feedback-aided scenarios. We explore a large subset of the family of linear lattice encoding methods, and we consider the two main families of decoders; maximum likelihood (ML) based and lattice-based decoding. Algorithmic analysis focuses on the efficient bounded-search implementations of these decoders, including a large family of sphere decoders. Specifically, the presented work provides high signal-to-noise (SNR) analysis of the minimum computational reserves (flops or chip size) that allow for a) a certain performance with respect to the diversity-multiplexing gain tradeoff (DMT) and for b) a vanishing gap to the uninterrupted (optimal) ML decoder or a vanishing gap to the exact implementation of (regularized) lattice decoding. The derived complexity exponent describes the asymptotic rate of exponential increase of complexity, exponential in the number of codeword bits.

No description available.

The past decade has shown distinct advances in the theory of multiple input multi output techniques for wireless communication systems. Now, the time has come to demonstrate this progress in terms of applications. This thesis introduces implementation of Schnorr- Euchner strategy based decoding algorithm applied on Altera system-on-chip (Stratix EP1S10F780C6) with Nios embedded processor. The lattice decoder is developed on FPGA using VHDL. The preprocessing part of algorithm is targeted for Nios embedded processor using C language. A controller is also designed to interface and communicate between the Nios embedded processor and lattice decoder.

In system-on-chips, system architecture designs greatly affect cost, performance, and power consumption of the systems. In system design time, we thus need to perform system architecture exploration. In order to effectively support architecture exploration, we improve de-efficiency of current architecture description languages and produce new ways of architecture description, including multiple architecture pattern descriptions and generalized coding description. Together with existing architecture description methods, we form a generalized architecture description language. In this thesis research, in order to support verification of designs in the generalized architecture description language, we designed its simulator software. The simulator should support the descriptions of the architecture description language, including structural description, behavioral description, coding description, multiple architecture pattern descriptions, and hardware data structures. We implemented the simulator software in several software modules, including simulator engine, parser design, interpreter design, generalized decoder design, multiple architecture pattern descriptions, and hardware data structures. We thus can effectively support the verification capability of the architecture description language.

The thesis is composed of two different IC design projects, which are briefly introduced as follows. The first topic is an area-saving decoder structure for ROMs. In this part of work, we propose a novel 3-dimensional decoding method. The stages of address decoding are drastically shortened. Hence, the delay is reduced as well as the power consumption. The overall transistor count and the delay are thoroughly derived. A physical 256x8 ROM using the proposed decoder is fabricated by UMC 0.5 mm 2P2M CMOS technology. The second part is the NIC (Network Interface Controller) design. The NIC transfers data frames from and to transmitter and receiver buffers in the host memory, respectively. Meanwhile, the transferred data must also comply with the IEEE 802.3 standard. The design is compatible with CSMA/CD type Local Area Network, including 10/100 Mbps Ethernet.