In recent years, LDPC codes are gaining a lot of attention among researchers. Its near- Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratied wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratied in 2005.<p> In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of congurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that veries the parity-check equations of the LDPC codes. Furthermore, a special characteristic of ve of the codes dened in the DVB-S2 standard and their in uence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near- Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratied wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratied in 2005.<p> In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of congurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that veries the parity-check equations of the LDPC codes. Furthermore, a special characteristic of ve of the codes dened in the DVB-S2 standard and their in uence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology.

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / The CNES (French Space Agency) has studied memoryless predistortion techniques for power amplifier nonlinearity of satellite payload telemetry. These techniques are applied to high order modulations taken from the DVB-S2 standard and the associated CCSDS blue book. An easy-to-implement calibration method was also developed. The predistortion was implemented at two times the symbol rate after Square Root Raised Cosine shaping on a breadboard model of a 16APSK modulator associated to a Solid State Power Amplifier. It allows to reduce the amplifier back-off and thus to increase the power added efficiency for an equivalent signal quality.

<p>Digital television is one of the biggest broadcasting media available. All over the world television companies are rearranging their broadcasting from analogue to digital transmission. Former standard disagreements in the analogue era have lead to an agreement of one common European standard for digital television. Countries like USA and Japan have their own similar standards.</p><p>The report consists of two objectives; a survey of the most commonly used standards for digital television today and the construction of a prototype receiver for the second generation satellite DVB-standard.</p><p>A thorough literature study and careful design resulted in a fully functioning system. Measurements performed on the DVB-S sections gave exemplary results. Comparing these results with corresponding measurements performed on the DVB-S2 section showed much better performance for DVB-S2 with the same code rates. This shows some of the advantages of the new standard and proving the coding theory right. New coding algorithms make it possible to transmit more information on noisier channels of inferior quality. In laymen’s words; DVB-S2 gives a better picture and more television channels on the same satellite compared to DVB-S.</p>

Σκοπός της συγγραφής της παρούσας διπλωματικής εργασίας είναι η μελέτη και ο σχεδιασμός της μονάδας συγχρονισμού φάσης σημάτων τεχνολογίας DVB-S2. Ο ρόλος της μονάδας αυτής είναι καθοριστικής σημασίας για την εξασφάλιση της αποδοτικής λειτουργίας των συστημάτων του προτύπου αυτού σε τυπικά δορυφορικά κανάλια. Αρχικά πραγματοποιείται μια εισαγωγή στις βασικές έννοιες και στη δομή ενός δορυφορικού συστήματος και εξετάζονται οι δυσμενείς επιδράσεις της ατμόσφαιρας κατά τη μετάδοση των δορυφορικών σημάτων. Ακολούθως γίνεται παρουσίαση της μετάδοσης τηλεοπτικών προγραμμάτων μέσω δορυφόρου και αναλύονται βασικά χαρακτηριστικά του δορυφορικού προτύπου DVB-S2. Παρουσιάζεται λεπτομερώς η αρχιτεκτονική μετάδοσής του και αξιολογείται η απόδοση του. Σημαντικό τμήμα της εργασίας αποτελεί η μελέτη του συγχρονισμού της παραμέτρου φάσης των λαμβανόμενων σημάτων σε δέκτες ψηφιακών συστημάτων επικοινωνίας. Αφού αναλυθεί η διαδικασία συγχρονισμού και τα χαρακτηριστικά της εκτίμησης της τιμής παραμέτρων των μεταδιδόμενων σημάτων, αναλύονται οι διατάξεις που υλοποιούν το συγχρονισμό φάσης σε σήματα τεχνολογίας DVB-S2 και εκτιμάται η απόδοσης λειτουργίας τους. Στη συνέχεια, περιγράφεται η διαδικασίας ανάπτυξης του μοντέλου υλοποίησης σε υλικό (FPGAs) της παραπάνω μονάδας, αξιοποιώντας το εργαλείο System Generator 10.1 της Xilinx και το περιβάλλον Simulink της Matlab. Τέλος, παρουσιάζεται και αναλύεται η ορθή λειτουργία της σχεδίασης για πραγματικά σήματα DVB-S2. / The purpose of this diploma thesis is the study and hardware implementation of Carrier Phase Recovery Unit for DVB-S2 systems. This operation of this unit of crucial importance complementing outstanding performance results over typical satellite channels. In the first part of this thesis, an introduction on important principles of satellite communications is carried out and the architecture of a satellite communication system is presented. Among others, the aggravating atmospheric effects taking place during satellite transmission are outlined. Afterwards, satellite transmission of television programs is examined and an analysis of the satellite standard DVB-S2 follows. The structural design of the transmission system is stated in detail and the efficiency of this standard is assessed. A substantial part of this work concerns the study of phase synchronization for digital communication receivers. After the theoretical analysis of the synchronization process, the unit implementing phase recovery for DVB-S2 systems is presented and its efficiency is examined for different kinds of distortions. Moreover, the procedure of hardware implementation (on FPGAs) of this unit is discussed, with the use of both Xilinx System Generator 10.1 and Simulink design tools. This thesis is concluded after presenting the efficient operation of the above implementation for real DVB-S2 signals.

Στην παρούσα διπλωματική εργασία παρουσιάζεται η υλοποίηση του συγχρονισμού ενός δορυφορικού δέκτη τεχνολογίας DVB-S2 με χρήση προϊόντων από την βιβλιοθήκη Xilinx του Simulink της Matllab. Αρχικά εξετάσαμε τη γενική συμπεριφορά ενός δέκτη και στη συνέχεια κατανοώντας τα ιδιαίτερα χαρακτηριστικά της τεχνολογίας DVB-S2, πραγματοποιήσαμε θεωρητική μελέτη του κυκλώματος που θα υλοποιήσουμε. Σαν επέκταση της παραπάνω μελέτης εξηγήσαμε δίνοντας παραδείγματα, για ποιους λόγους σε κάθε σημείο του συγχρονιστή επελέχθη το εκάστοτε υλισμικό-λογισμικό, από θεωρητικής άποψης. Έπειτα μας δόθηκε ένα μοντέλο, το οποίο ήταν υλοποιημένο με προϊόντα από την γενική βιβλιοθήκη (Simulink) της Matllab· στη συνέχεια δημιουργήσαμε ύστερα από διεξοδικά πειράματα και συγκρίσεις ένα μοντέλο, υλοποιημένο με προϊόντα από τη βιβλιοθήκη Xilinx του Simulink της Matllab, με συμπεριφορά ίδια με αυτή του μοντέλου που μας δόθηκε. Τέλος, παρουσιάσαμε μέσω γραφικών παραστάσεων και γραφημάτων τόσο τη σύγκριση της συμπεριφοράς των δυο μοντέλων, όσο και τη λειτουργία και τις ιδιαιτερότητες αυτού καθ’ εαυτού του μοντέλου που δημιουργήσαμε. / In this diplomatic work we present the concretization of timing of satellite receptor of technology DVB-S2 with use of products from the library Xilinx of Simulink of Matlab. Initially we examined the general behavior of receptor and afterwards comprehending the particular characteristics of technology DVB-S2, we realized theoretical study of circuit that we will materialize. As extension of previous study we explained giving examples, for what reasons we chose each hardware-software, from theoretical point of view. Then we were given a model, which was materialized with products from the general library (Simulink) of Matllab; afterwards we created after extensive experiments and comparisons, a model, materialized with products from the library Xilinx of Matllab Simulink, with behavior precisely same with that of model that was given to us. Finally, we presented via graphic representations and illustrations both the comparison of behavior of two models, and the operation and the particularities each one of the models we created.

Les retours et les études dont on dispose sur les réseaux IP par satellite ne permettent pas d’apprécier les performances dont ils sont capables. Pourtant, les difficultés de transmettre de l’IP par satellite persistent encore. L’inadaptation du protocole IP, initialement conçu pour des réseaux terrestres, au large produit délai-bande du média satellite est une raison. Le fonctionnement souvent dé-corrélé entre les niveaux supérieurs de la pile TCP/IP et les couches physique et MAC du média satellite, est une autre. Dans le cadre de ce travail de thèse nous adoptons une démarche expérimentale basée sur l’observation, l’analyse et l’évaluation de systèmes implantant des technologies IP par satellite tels que le standard DVB-RCS, la technologie propriétaire iDirect ou la nouvelle norme DVB-S2. Nous étudions l’impact des règles de qualité de service IP sur les performances des applications dans un contexte de bande limitée. Nous nous penchons notamment sur l’évaluation des efficacités de l’encapsulation IP en termes de consommation de bande. Notre premier objectif est de déceler les niveaux auxquels un opérateur peut agir en vue d’optimiser la configuration d’un système IP par satellite et en accroître les performances / Despite of a number of IP satellite networks developed and deployed, only a limited number of studies and feedbacks about the performance is available. IP over satellite systems raises several constraints. One of the main reasons is the lack of adaptation of IP protocol, initially designed for terrestrial wired networks, to the large bandwidth delay product of the satellite media. Another reason is a lack of coordination between the IP protocol stack upper layer and the satellite MAC and physical layer. The purpose of this PhD study is to evaluate and assess the behaviour of IP applications when conveyed over satellite systems. We mainly focus on the IP quality of service performance, bandwidth encapsulation efficiency as well as IP applications metrics. Through the observation, we try to find how it’s possible to modify the IP satellite systems configuration in order to improve IP applications performance. We also suggest some ideas about the way to refine these technologies with regards to the design aspects. Experimentations have been performed over test beds implementing both standardised satellite technologies such as DVB-RCS as well as proprietary systems such as iDirect in addition to the new normalised technology DVB-S2

Nos travaux de thèse ont pour objectif la conception, la mise en Suvre et l'évaluation d'architectures pour la mobilité et la qualité de service (QoS) dans des systèmes satellites DVB-S2/RCS. Ces systèmes peuvent constituer une solution alternative efficace aux réseaux terrestres dans des zones reculées à faible densité de population mais ils doivent pour cela offrir les mêmes services tout en tenant compte de leurs caractéristiques spécifiques, en particulier leur long délai de transmission qui peut s'avérer problématique dans le cadre d'applications multimédias interactives. Notre première contribution a donc été de développer une architecture de QoS adaptée à ce type d'applications, utilisant le modèle DiffServ et se basant essentiellement sur l'interaction entre l'architecture liée au protocole d'initiation de session SIP et différentes entités du système satellite. La QoS peut alors être configurée de façon précise au niveau des STs, par le biais de l'outil TC, en analysant les descripteurs de session SDP compris dans les messages SIP et en déduisant leurs caractéristiques (débit, gigue max, délai max, etc...) soit localement si elles sont connues, soit à partir d'un service Web que nous avons développé. Nous avons ensuite proposé et développé une solution de mobilité basée sur SIP, adaptée au système satellite ainsi qu'à la solution de QoS précédemment décrite. Les performances de cette solution ont alors été comparées, en termes de temps d'interruption et de consommation de ressources, avec celles obtenues par Mobile IPv6 et certaines de ses extensions, démontrant ainsi de réelles améliorations pour le cas des applications multimédias interactives. Enfin, notre dernière contribution a été de développer deux architectures couplant QoS et mobilité, une spécifiquement conçue pour les applications interactives et basée sur la combinaison de notre solution de mobilité SIP avec notre architecture de QoS SIP et une autre basée sur Mobile IPv6 ou FMI Pv6 et sur l'interaction d'un QoS Agent mobile avec les entités de QoS du système satellite. Ces architectures ont été évaluées et comparées sur la plateforme d'émulation PLATINE développée dans le cadre du projet SATSIX.