This dissertation studies a unique delta sigma modulator (DSM), known as reversed hysteresis delta sigma modulator (R-HDSM). This modulator is appropriate for ultra-high speed analog-to-digital converters, which can be used for communications and signal processing systems and their applications. Furthermore, the procedure to design the binary delta sigma modulator (BDSM) with a delay is developed and then parameters deltaOFF and deltaON ; are calculated for the system. In addition, analysis of the BDSM with a delay is achieved and the theoretical and simulated values compared. The reversed hysteresis delta sigma modulators are also analyzed, and the theoretical and the simulated values compared. The dissertation evaluates the performance measure for the suggested systems with continuous DSM and BDSM in terms of the spurious free dynamic range (SFDR), the signal to noise ratio (SNR), and the root mean square error (RMS). It studies the second-order R-HDSM. Finally, it compares the first-order R- HDSM and the second-order R-HDSM in terms of the signal to noise ratio (SNR).

In this thesis, the design of a scaling-friendly continuous-time closed-loop voltage controlled oscillator (VCO) based Delta-Sigma analog to digital converter (ADC) is introduced. It uses the VCO as both quantizer and integrator, and thus, obviates the need for power-hungry scaling-unfriendly operational transconductance amplifiers (OTAs) and precision comparators. It arranges two VCOs in a pseudo-differential manner, which cancels out even-order distortions. More importantly, it brings an intrinsic clocked averaging (CLA) capability that automatically addresses digital to analog converter (DAC) mismatches. The prototype ADC in 130 nm complementary metal-oxide-semiconductor (CMOS) occupies a small area of 0.03 mm² and achieves 66.5 dB signal to noise and distortion ratio (SNDR) over 2 MHz bandwidth (BW) while sampling at 300 MHz and consuming 1.8 mW under a 1.2 V power supply. It can also operate with a low analog supply of 0.7 V and achieves 65.8 dB SNDR while consuming 1.1 mW. The corresponding figure-of-merits (FOMs) for the two cases are 0.25 pJ/conversion-step and 0.17 pJ/conversion-step, respectively. / text

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

With today’s technology, digital signal processing plays a major role. It is used widely in many applications. Many applications require high resolution in measured data to achieve a perfect digital processing technology. The key to achieve high resolution in digital processing systems is analog-to-digital converters. In the market, there are many types ADC for different systems. Delta-sigma converters has high resolution and expected speed because it’s special structure. The signal-to-noise-and-distortion (SINAD) and total harmonic distortion (THD) are two important parameters for delta-sigma converters. The paper will describe the theory of parameters and test method.

Low intrinsic transistor gain in nanometer CMOS technologies imposes implementation difficulties of switched-capacitor (SC) circuits based on a conventional OTA used in delta-sigma ADCs. Zero-crossing-based circuits (ZCBCs) have been proposed as replacements for conventional OTAs in SC circuits, but the efficiency of existing ZCBC-based delta-sigma ADCs trails that of state-of-art conventional delta-sigma ADCs. The dynamic comparator-based OTA (DCBOTA) is a novel circuit block that performs an equivalent operation of a conventional OTA in a SC circuit by repeatedly detecting the input (Vg) sign and applying output current pulses to move Vg toward zero. The current pulse amplitude, set to the maximum at the beginning of a charge transfer phase, is decremented each time Vg crosses zero. Once Vg crosses zero at the minimum current pulse amplitude, the operation above ceases. The discrete-time nature of Vg comparison and current pulse injection in the DCBOTA allows use of a dynamic regenerative comparator, which is fast and scaling friendly, instead of the slow scaling-unfriendly open-loop zero-crossing detector used in ZCBCs. A small final Vg step size is required for high settling accuracy, but it can result in a long settling time. Analysis reveals that the DCBOTA settling time is minimized with a current pulse scaling factor of 3.59 for any final Vg step size. The comparator and switch noise affects the settling DCBOTA settling accuracy. The relationship between the minimum Vg step size, comparator noise, and switch noise for a given input-referred noise is shown. The DCBOTA consists of a dynamic regenerative comparator, control logic, and current pulse driver. The comparator evaluates the Vg sign when enabled by the control logic. The control logic enables and resets the comparator, and controls the current pulse amplitude. The current pulse driver applies either a positive or negative output current pulse when triggered by the comparator output. A 1-1-1-1 MASH delta-sigma ADC using DCBOTAs fabricated in a 65-nm CMOS technology achieved 70.4 dB of peak SNDR over a 2.5-MHz bandwidth dissipating 3.89 mW of power from a 1.2-V supply. Measurements show linear ADC power scaling over sampling frequencies provided by the dynamic operation of the DCBOTAs.

In this research an approach to design and implement all-optical delta-sigma modulator (ODSM) has been expanded. The two main blocks of this modulator are “leaky integrator” and “bi-stable switch” designed and implemented by using active element like semiconductor optical amplifier (SOA) and other passive elements like optical filter, isolator and coupler. All experiments are done on optical table and proper results achieved. Thus the new bi-stable switch is designed and implemented by using “inverted bistable switch” and “non-inverted bi-stable switch”. This switch is made by five ring lasers. Right wavelengths have chosen for each ring laser to achieve a novel characteristic called “Proteresis”. All control parameters of this switch was investigated The major impact of this research will be in the area communication system, which need high resolution and fast modulation speed with less noise in their systems.

As the rapid evolution in semiconductor technology, transistors’ feature size has reached to 22nm and below, which brings great impact to analog and mixed-signal circuits. As the significant bridge connecting the analog world and digital system, data converter suffers from nonlinearity resulting from mismatch among its unit components. The smaller transistors are, the larger relative mismatch among them becomes. However, using larger transistors leads to more area cost and power consumption. Therefore, researchers have been working hard on how to alleviate the mismatch issue. In recent years, Dynamic Element Matching (DEM) becomes a popular approach that can significantly improve linearity, especially Spurious-free Dynamic Range (SFDR), of a data converter system. The basic idea of DEM is to shuffle the usage pattern of unit elements so that the mismatch error is no longer correlated to the input signal. Thus, DAC’s linearity will be improved. Generally, DEM Nyquist-rate DAC does mismatch scrambling, which smooths distortions resulting from mismatch into white noise. DEM Delta-Sigma DAC does mismatch shaping, which pushes distortions away from the signal band, typically lower frequencies. In this thesis, we focused on mismatch-shaping Delta-Sigma DACs. Two of those various algorithms are implemented logically and physically. With placement and routing information, we got more accurate result on the speed and power dissipation. The comparison shows the tradeoff among number of quantization levels, mismatch-shaping order, and hardware complexity. / text

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1.67kS/s.

In this thesis, a 14-bit low-power Analog-to-Digital Converter (ADC) is designed for sensor applications. Following on previous work, the ADC is designed to be frequency scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, class AB opamps are used. The design was fabricated in 0.18um CMOS and occupies an area of 0.35mm2. Operating at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83uW. In incremental mode, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 89dB peak SNDR while operating from 1.67S/s to 1.67kS/s.

In this proposal, an advanced local oscillator with high resolution, low phase noise and fast switching characteristics is designed for wireless communication applications. The circuit is based on fractional-N frequency synthesis technique in which the use of delta-sigma modulator can remove the fractional spurs effectively. The mechanism in regard to fractional spurs and phase noise for a fractional-N frequency synthesizer will be studied and simulated by developing proper mathematical models. In the implementation of the local oscillator, the analog circuit includes a 1000-1033 MHz VCO, crystal oscillator and loop filter. The digital circuit includes a phase frequency detector, dual modulus divider and 3rd order delta-sigma modulator. At first a FPGA will be used to prototype the digital circuit. The final digital circuit will be implemented in a CMOS process and require 3V operation with low current consumption. The design specifications include that under 1 KHz resolution the phase noise levels are less than -90 dBc/Hz at frequency offets within a loop bandwidth more than 100 KHz. Spurious components are less than -90 dBc/Hz and switching time is less than 1 ms over a 30 MHz tuning range.