This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

abstract: In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any offset and subtract out if necessary, and an automatic startup and manual calibration to control the common mode voltages. The proposed ADC was designed in Intel’s 10nm technology. This ADC is designed to monitor DC voltages for the precision and high speed applications. The conversion rate of the analog to digital converter is programmable to 7µs or 910ns, depending on the precision or high speed application, respectively. The range of the input and reference supply is 0 to 1.25V. The ADC is designed in Intel 10nm technology using a 1.8V supply consuming an area of 0.0705mm2. This thesis explores challenges of designing a dual-purpose analog to digital converter, which include: 1.) increased offset in 10nm technology, 2.) dual application ADC that can be accurate and fast, 3.) reducing the parasitic capacitance of the ADC, and 4.) gain error that occurs in ADCs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Tato diplomová práce si klade za cíl seznámit čtenáře se základním konceptem a principy jednosmyčkových modulátorů . Diplomová práce ozřejmuje čtenáři problematiku delta-sigma () modulátorů s jednou zpětnovazební smyčkou. Zabývá se základními principy převzorkování u číslicově-analogových převodníků a rozšiřuje je o teorii tvarování spektra šumu. Vycházeje z této teorie jsou navrženy tři jednosmyčkové modulátory, které běží na 1024 OSR jako alternativa k běžně používáným modulátorům vysokých řádů. Modulátory jsou implementovány do FPGA společně s rekonstrukčním filtrem a podpůrnými bloky. Nakonec byl zkonstruován hardwarový prototyp pro vyhodnocení implementace navrženého DAC.

The thesis deals with an influence of the errors caused by utilization of the switched-current (SI) approach in the delta-sigma modulators. The basic block of the SI technique is current memory cell (CMC). The analysis of the errors starts with the design of the CMC using CADENCE software and AMIS CMOS 0.7 um technology. Based upon analysis of the CMC no ideal transfer function and advanced techniques of their behavior modeling are depicted. The mathematical models were made and implemented using MATLAB SIMULINK software. The models are very universal. Therefore, it is possible to analyze various structures of the delta-sigma modulators using demanded technology. The influence of the SI technique approach errors sources, on the modulators behavior with the CMC of the 1st and 2nd generation, is concluded at the end.

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

abstract: This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW power. Another example achieves 78.2dB SNR in 31.25µs measurement time and consumes 63µW power. The second ADC architecture is a multi-mode, dynamically zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)- independent, dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW power consumption from a 1.2 V supply. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

This dissertation is a contribution toward developing all-optical binary delta sigma modulator (BDSM) [‎27] by changing its bistability to proteretic bistability in order to increase the modulator bandwidth frequency. An innovative delta sigma modulator called proteretic binary delta sigma modulator (PBDSM), which is optically compatible, is investigated theoretically and by modeling and simulation and its bandwidth superiority is proven. The time interval of PBDSM Δt calculation is driven and dynamic performance measure of PBDSM comparing to previous related work is computed, modeled and simulated. Modeling and simulations are based on Matlab-Simulink for ideal environment testing. The basic components of BDSM are the leaky integrator and the bi-stable device. Thus, the focus was on improving the bi-stable device to overcome the bandwidth limitation toward THz modulation frequency in optical domain. Consequently, proteresis bistability was investigated in semi-practical domain, using Matlab-Simulink function, for clear realization of its input-output characteristics and compared with the corresponding hysteresis bistability. The contribution in this research, regarding proteresis bi-stable device design, can be implemented in current technologies, both optical and electrical, of continuous-time delta sigma modulation. Furthermore, the new design showed capability and more flexibility in manipulating its output form and it showed more control on the way of conducting delta sigma modulator error correction.

Le marché des convertisseurs analogique-numérique peut être segmenté en deux catégories de circuits. Nous distinguons d’une part, les blocs de propriété intellectuelle (IP) qui sont généralement optimisés pour une application spécifique. Et d’autre part, les circuits intégrés discrets qui sont conçus pour répondre aux besoins d’une plus large gamme d’applications. Ce travail de thèse concerne la deuxième catégorie de composants. Il s’inscrit dans le cadre d'un programme de recherche et développement initié en 2010 dans le projet européen FP7 SACRA et dont le but était d'étudier la faisabilité d'un convertisseur analogique-numérique Delta-Sigma (DS) qui pourrait rivaliser avec l'architecture pipeline pour des applications nécessitant une large bande passante (≥10MHz) et une haute résolution (>10-bit) comme l’imagerie médicale, les communications numériques sans fils ou câblées, la vidéo ou encore l’instrumentation. Ce manuscrit synthétise les travaux de conception, fabrication et mesure d’un modulateur DS Passe-bas à temps continu avec une bande passante de 40MHz, et visant une résolution effective de 12-bit tout en consommant moins de 100mW. / The market of A/D converters can be segmented in two categories. From one side we distinguish the Intellectual Property (IP) blocks that are generally optimized for a specific application. On the other side, the general-purpose discrete Integrated Circuits (ICs) that are designed such as they could be used in different applications. This thesis work deals with the second category. It is part of a research and development program initiated in 2010 in the European project FP7 SACRA, whose purpose was to study the feasibility of a delta-sigma (DS) analog-to-digital converter that could compete with the pipeline architecture for applications that require high bandwidth (≥10MHz) and high resolution (>10-bit) such as medical imaging, wireless and wireline communications, video or instrumentation. Currently, the pipeline is still largely predominant for such applications and the few commercial wideband solutions based on a DS architecture have a signal bandwidth limited to 10 MHz or 25 MHz while consuming respectively 100mW and 20mW for an ENOB around 12-bit. This manuscript summarizes the design, fabrication and measurement of a low-pass CT DS modulator with a signal bandwidth of 40MHz, while targeting an effective resolution of 12-bit and a power consumption of less than 100mW.

No description available.

<p>Background:</p><p>The task of this thesis is to investigate the possibility of using non-linear high efficiency switching power amplifiers with spectrally efficient varying envelope modulation schemes and, if possible, further investigate such a solution on a high level.</p><p>The thesis focuses on the theory necessary to understand the technical issues related to power amplifiers and the procedures behind simulating and measuring the characteristics of different power amplifier configurations. The thesis also covers basic theory behind Delta-Sigma-modulators. The theory is needed to draw conclusions about the feasibility of using a Delta-Sigma-modulator as input to a switching amplifier.</p><p>Results:</p><p>Using a Delta-Sigma-modulated input to a switching amplifier inherently degrades the performance, mainly because of poor coding efficiency and high switching activity. However, by merely using a switching amplifier as a mixer it is shown to be possible to transmit a non-constant envelope signal, with digital logic. The resulting circuit is, however, not an amplifier and it should not be seen as the final result. As already mentioned: the result lies in the investigation of a using Delta-Sigma-modulator as input to a switching amplifier.</p><p>Conclusion:</p><p>From this investigation we believe that the widely known technique: pulse width modulation (PWM), together with a tuned switching amplifier and some linearization technique, for example pre-distortion, is a better way to go. Much effort should be put in understanding the fundamental limits and possibilities of an efficient tuned switching power amplifier.</p>