The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed. / text

An ISM-band frequency synthesizer is introduced in this thesis. The technique allows digital phase/frequency modulation to be achieved in a closed phase locked loop (PLL) without mixers and D/As. According to the simulation results using ADS, quantization noise will be filtered by the PLL bandwidth. But the data rate is also bounded by the PLL bandwidth. Two key components of this closed-loop architecture, Gaussian filter and delta-sigma modulator have been implemented by FPGA together with the Qualcomm Q3236 synthesizer IC.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.

In the first, a time-variant modulus phase lock loop(PLL) model is established. Applying the model, Theorems of fractional-N synthesizers are introduced. We also explain theorems and simulations of Closed-Loop Modulation and Two-Point Delta Sigma Modulation with the model. In the end, a 2.4GHz FHSS transmitter using Two-Point Delta Sigma Modulation which meets Bluetooth specifications is demonstrated.

The recent trend in the RF and microwave industry has been a move towards increasing the number of components realized on one radio frequency integrated circuit (RFIC) (or microwave integrated circuit (MIC)). This trend has resulted in complex RFICs which often require reactive as well as other circuit components to be supplied in the form of an external circuit. Because the manufacturer's suggested circuit is often developed with a specific application in mind, the same circuit may not satisfy the demands of another application. Provided the necessary functionality and connections are possible, the external circuit may be altered such that the requirements of the other application can be met, thus extending the flexibility of the RFIC. The work presented here is focused on investigating modifications to RF Microdevices' suggested external circuit for the RF29X5 family of low cost, half duplex, FM/AM/ASK/FSK RFIC transceivers originally intended for operation in the 433, 868, or 902-928 MHz industrial, scientific, and measurement (ISM) bands. Examinations of the operating principles of the transceiver components were performed which facilitated the identification of suitable modifications. Among the modifications identified were implementation of a phase locked detector, various methods for extending the FSK data rate limitations of the transmitter, improving the phase noise of the VCO, and the implementation of a fractional-N synthesizer using the RF2905 internal phase-locked loop (PLL) components and external inexpensive logic circuits. In addition to these modifications to the external circuit, the investigation of the oscillators of the RF2905 resulted in a potentially improved implementation of the VCO by modifying the internal active circuitry as well. / Master of Engineering

This dissertation presents a 2.4 GHz wideband GFSK-modulated frequency synthesizer using two-point delta-sigma modulation (TPDSM). The two bottlenecks in this design have been rigorously investigated. One bottleneck is the nonlinear performance of the phase-locked loop (PLL). The other one is the inherent gain and delay mismatch between the two modulation points. Both nonlinear and mismatch factors dominate the modulation accuracy in the closed PLL. The proposed formulation can successfully predict the dependencies of the modulation accuracy on both factors. The comparison of the averaged frequency deviation and frequency-shift -keying (FSK) error between theory and measurement shows excellent agreement. The modulated frequency synthesizer implemented in this study can achieve a 2.5 Mbps data rate as well as a 15 £gs PLL stable time with only 2.2 % FSK error under good design and operating conditions.

This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

Wireless communication systems are based on frequency synthesizers that generate carrier signals, which are used to transmit information. Frequency synthesizers use voltage controlled oscillators (VCO) to produce the required frequencies within a specified period of time. In the process of generating frequency, the VCO and other electronic components such as amplifiers produce some unwanted short-term frequency variations, which cause frequency instability within the frequency of interest known as phase noise (PN). PN has a negative impact on the performance of the overall wireless communication system. A literature study conducted on this research reveals that the existing PN cancellation techniques have some limitations and drawbacks that require further attention. A new PN correction technique based on the combination of least mean square (LMS) adaptive filtering and single-loop single-bit Sigma Delta (SD) modulator is proposed. The new design is also based on the Cascaded Resonator Feedback (CRFB) architecture. The noise transfer function (NTF) of the architecture was formulated in way that made it possible to stabilize the frequency fluctuations within the in-band (frequency of interest) by locating its poles and zeros within the unit circle. The new design was simulated and tested on a commercially available software tool called Agilent Advanced Design System (ADS). Simulation results show that the new technique achieves better results when compared with existing techniques as it achieves a 104 dB signal-to-noise (SNR), which is an improvement of 9 dB when compared with the existing technique accessed from the latest publications. The new design also achieves a clean signal with minimal spurious tones within the inband with a phase noise level of -141 dBc/Hz (lower phase noise level by 28 dBc/Hz) when compared with the existing techniques. / Thesis (MEng)--University of Pretoria, 2017. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. The approach provides fine resolution and wide bandwidth as well as low phase noise and should find application in many contemporary communication systems. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs when operated in the second mode. For example, in an application to a P-GSM 900 system, it is capable of tuning from 890 – 915 MHz with a channel spacing of 200 kHz and shows worst case phase spurs of -100 dBc at an offset frequency of 833 kHz. Because of the low magnitude and location of the worst case spurs, the phase-locked loop filters can be designed with a wide bandwidth which in turn results in a fast settling time. A linear frequency-switching settling time (to 0.01% of frequency increments) of 128 μs is typical in the P-GSM 900 application.