With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

A fully integrated, fast-locking fractional-N frequency synthesizer is proposed and demonstrated in this work. In this design, to eliminate the need for large, inaccurate capacitors and resistors in a loop filter, an analog continuous-time loop filter whose performance is sensitive to process and temperature variations and aging has been replaced with a programmable digital Finite Impulse Response (FIR) filter. In addition, using the adaptive loop gain control proportional to the frequency difference, the frequency-locking time has been reduced. Also, the phase noise and spurs have been reduced by a Multi-stAge noise SHaping (MASH) controlled Fractional Frequency Detector (FFD) that generates a digital output corresponding directly to the frequency difference. The proposed frequency synthesizer provides many benefits in terms of high integration ability, technological robustness, fast locking time, low noise level, and multimode flexibility. To prove performance of the proposed frequency synthesizer, the frequency synthesizers analysis, design, and simulation have been carried out at both the system and the circuit levels. Then, the performance was also verified after fabrication and packaging.

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Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted