ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / This paper describes the use of an efficient FPGA design flow, called Ogre, developed at BYU to design and implement PCM/FM demodulators. Ogre exploits the notion of reuse by taking advantage of a library of specially designed cores parameterized by XML metadata. A judicious choice of library cores, targeted to signal processing functions common to sampled data modulators and demodulators, reduces the design and test cycle time. We demonstrate this by using the tool to construct rapid prototypes of three different versions of FM demodulators and show that the bit error rate performance is comparable to demodulators on the market today.

The success of deep learning has renewed interest in applying neural networks and other machine learning techniques to most fields of data and signal processing, including communications. Advances in architecture and training lead us to consider new modem architectures that allow flexibility in design, continued learning in the field, and improved waveform coding. This dissertation examines neural network architectures and training methods suitable for demodulation in power-limited communication systems, such as those found in wireless sensor networks. Such networks will provide greater connection to the world around us and are expected to contain orders of magnitude more devices than cellular networks. A number of standard and proprietary protocols span this space, with modulations such as frequency-shift-keying (FSK), Gaussian FSK (GFSK), minimum shift keying (MSK), on-off-keying (OOK), and M-ary orthogonal modulation (M-orth). These modulations enable low-cost radio hardware with efficient nonlinear amplification in the transmitter and noncoherent demodulation in the receiver. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2020. / FAU Electronic Theses and Dissertations Collection

The objective of this research is to develop and design front-end analog circuits for Capacitive Micromachined Ultrasound Transducers (CMUTs) and optical grating MEMS microphone. This work is motivated by the fact that with micro-scaling, MEMS sense capacitance gets smaller in a CMUT array element for intravascular ultrasound imaging, which has dimensions of 70um x 70um and sub pico-farad capacitance. Smaller sensors lead to a lower active-to-parasitic ratio and thus, degrads sensitivity. Area and power requirements are also very stringent, such as the case of intravascular catheter implementations with CMOS-First CMUT fabrication approach. In this implementation, capacitive feedback charge amplifier is an alternative approach to resistive feedback amplifiers. Capacitive feedback charge amplifier provides high sensitivity, small area, low distortion and saving power. This approach of charge amplifiers is also suitable in capacitive microphones where it provides low power and high sensitivity. Another approach to overcome capacitive detection challenges is to implement optical detection. In the case of biomimetic microphone structure, optical detection overcomes capacitive detection's thermal noise issues. Also with micro-scaling, optical detection overcomes the increased parasitics without any sensitivity degradation, unlike capacitive detection. For hearing aids, along with sensitivity, battery life is another challenge. We propose the use of 1-bit front-end sigma-delta ADC for overall improved hearing aid power efficiency. Front-end interface based on envelope detection and synchronous detection schemes have also been designed. These interface circuits consume currents in microampere range from a 1.5V battery. Circuit techniques are used for maximizing linear range and signal handling with low supplies. The entire front end signal processing with Vertical Cavity Surface Emitting Laser (VCSEL) drivers, photodiodes, filters and detectors is implemented on a single chip in 0.35um CMOS process.