This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

The cochlea is an organ which extracts frequency information from the input sound wave. It also produces nerve signals, which are further analysed by the brain and ultimately lead to perception of the sound. An existing model of the cochlea by Fragni`ere is first analysed by simulation. This passive model is found to have the properties that the living cochlea does in terms of the frequency response. An analog VLSI circuit implementation of this cochlear model in CMOS weak inversion is proposed, using log-domain filters in current domain. It is fabricated on a chip and a measurement of a basilar membrane section is performed. The measurement shows a reasonable agreement to the model. However, the circuit is found to have a problem related to transistor mismatch, causing different behaviour in identical circuit blocks. An active cochlear model is proposed to overcome this problem. The model incorporates the effect of the outer hair cells in the living cochlea, which controls the quality factor of the basilar membrane filters. The outer hair cells are incorporated as an extra voltage source in series with the basilar membrane resonator. Its value saturates as the input signal becomes larger, making the behaviour rather closer to that of a passive model. The simulation results show this nonlinear phenomenon, which is also seen in the living cochlea. The contribution of this thesis is summarised as follows: a) the first CMOS weak inversion current domain basilar membrane resonator is designed and fabricated, and b) the first active two-dimensional cochlear model for analog VLSI implementation is developed.

Recently, with advances in CMOS process, the RF receiver which is integrated into the SOC chip can effectively reduce production costs. When designing the wireless receiver, one of the most important technologies is to design channel-selection filter. Typically, the design of the channel-selection filter in multi-standard high-frequency will take up a large chip area and higher power consumption. Therefore, in order to reduce the area and power consumption, this thesis designed a low-power OTA and low-pass filter. This thesis presents a multi-mode wireless communication application in the receiver channel selection filter. This filter is designed to use the fifth-order Butterworth low pass filter, the filter range can be used in Bluetooth, cdma2000, wideband CDMA, and IEEE 802.11a/b/g/n wireless LAN. Using floating transistor architecture in the input stage of OTA can effectively increase the THD performance. Using MOS transistors operating in triode region and combined with current multiplier can achieve the voltage-to-current conversion. Using the trans-linear loop can reach a wide tunable range, and the OTA operating in weak inversion region can significantly reduce the transconductance. Implementation is to use the TSMC 0.18£gm CMOS process. Simulation results show that the successful operation of this filter can be between 650 kHz ~ 22MHz frequency range. The filter may have compatibility in different wireless communication applications. 14.5mW to 17.5mW, respectively, is the smallest to the largest power consumption. The supply voltage is 1.2 volts.

The cochlea is an organ which extracts frequency information from the input sound wave. It also produces nerve signals, which are further analysed by the brain and ultimately lead to perception of the sound. An existing model of the cochlea by Fragni`ere is first analysed by simulation. This passive model is found to have the properties that the living cochlea does in terms of the frequency response. An analog VLSI circuit implementation of this cochlear model in CMOS weak inversion is proposed, using log-domain filters in current domain. It is fabricated on a chip and a measurement of a basilar membrane section is performed. The measurement shows a reasonable agreement to the model. However, the circuit is found to have a problem related to transistor mismatch, causing different behaviour in identical circuit blocks. An active cochlear model is proposed to overcome this problem. The model incorporates the effect of the outer hair cells in the living cochlea, which controls the quality factor of the basilar membrane filters. The outer hair cells are incorporated as an extra voltage source in series with the basilar membrane resonator. Its value saturates as the input signal becomes larger, making the behaviour rather closer to that of a passive model. The simulation results show this nonlinear phenomenon, which is also seen in the living cochlea. The contribution of this thesis is summarised as follows: a) the first CMOS weak inversion current domain basilar membrane resonator is designed and fabricated, and b) the first active two-dimensional cochlear model for analog VLSI implementation is developed.

This thesis presents four-quadrant CMOS current-mode multiplier architectures based on the bipolar Gilbert cell multiplier architecture. Multipliers are designed using the CMOS subthreshold region to take advantage of the subthreshold exponential I-V relationship that closely matches bipolar modeling. It is discovered that biasing to remove drift current components and to address higher order effects such as ideality factor mismatch, threshold mismatch, body effect, and short channel effects, is important to provide a linear multiplier. It is also shown that distortion caused by device size mismatch and offset input currents can be used to cancel the distortion introduced by drift currents when designing in weak and moderate inversion. This concept allows for linear multiplier designs with larger input currents which results in dramatic improvements in bandwidth over traditional weak inversion circuits. Three multiplier circuits are simulated and fabricated in an AMIS 0.35-um process. Circuits with less than 1 % nonlinear error and distortion (THD) across 100 % dynamic input range and with bandwidths greater than 100 MHz can be built. Also, low power multiplier solutions are presented that consume less than 40 nW of dynamic power.

This thesis demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high gain (113 dB) and low-power op amp (28.1 µW). The circuit can be fabricated without adding a compensation capacitance. The advantages of this architecture include high voltage gain, low bandwidth, low harmonic distortion, low quiescent current and power, and small chip area. These advantages suggest that this design might be well-suited for biomedical applications where low power, low noise bio-signal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range is required.

Les fluctuations électriques des composants sont une limitation à la miniaturisation des circuits. Malgré des procédés de fabrications en continuelle évolution, les variations des caractéristiques électriques dues au désappariement entre deux dispositifs limitent les performances des circuits. Concernant les applications à faible consommation, ces fluctuations locales peuvent devenir très critiques. Dans le contexte du développement d’une technologie CMOS 90nm avec mémoire Flash embarquée pour des applications basse consommation, l’appariement de transistors MOS est étudié. Une analyse de l’impact du dopage de grille des transistors NMOS est menée. L’étude se focalise sur l’appariement en tension des paires différentielles polarisées dans la zone de fonctionnement sous le seuil. Il est démontré que cet appariement peut être dégradé à cause de l’effet « hump », c'est-à-dire la présence de transistors parasites en bord d’active. Un macro-modèle permettant aux concepteurs de modéliser cet effet est présenté. Il est étudié au niveau composant, au niveau circuit et en température. Enfin, une étude de la dégradation de l’appariement des transistors MOS sous stress porteurs chauds est réalisée, validant un modèle de dégradation. Des transistors octogonaux sont proposés pour supprimer l’effet « hump » et donnent d’excellents résultats en termes d’appariement ainsi qu’en fiabilité. / Electrical fluctuations of devices limit chip miniaturization. Despite manufacturing processes in continuous evolution, circuit performances are limited by electrical characteristics variations due to mismatch between two devices. Concerning low power applications, local fluctuations can become very critical. In the context of development of a 90nm CMOS technology with Embedded Flash memory for low power applications, MOS transistors matching is studied. A study of NMOS transistors gate doping impact is conducted. Study focuses on voltage matching of differential pairs biased under threshold. It is demonstrated that this matching can be degraded due to « hump » effect, meaning presence of parasitic devices on active edge. A macro-model allowing designers to model this effect is presented. It is studied at device level, circuit level and for different temperatures. Finally, a degradation study of MOS transistors mismatch under Hot Carriers Injection stress is performed, validating a degradation model. Octagonal devices are proposed to suppress « hump » effect and give good results in terms of matching as well as reliability.

The electronics industry has developed incredibly in last few years and the need for low voltage and low power consuming devices is reflected with its growth. A small extension in battery life can be reflected in an order of magnitude in terms of retail prices. From multimedia gadgets (like laptops, mobiles, notebook etc.) to the biomedical device, all applications have seen a rapid advancement. All these devices need a low voltage and low power transceiver to connect with the wireless networks. This PhD thesis is focused on the development of new designing techniques for low voltage, low power integrated circuits, having close attention on circuits suitable for analog devices. The vast majority of high performance analog circuit cells realized in metal–oxide–semiconductor field-effect transistor (MOSFET) technologies traditionally exploits transistors operating in saturation. Meanwhile there exists a region of weak inversion, which was left unexploited until recently, where the behavior of a MOS transistor is similar to a bipolar transistor in qualitative terms. This region could be exploited for the devices which require operating with low voltage supply. Instead of operating in saturation region, the MOS devices employed in this design, operate in weak inversion. The MOS devices in the proposed circuits are bulk-controlled. In the conventional mode of biasing the bulk terminal is left unused and is connected with lowest supply voltage or ground while the gate is usually chosen for the input signal introduction to bias the circuit. The bulk can be used as an input for signal, can lower the threshold of a transistor if biased properly, ultimately lowering the supply voltage requirement of the transistor. In this work a modified Nauta’s Transconductor, which operates on very low voltages and have a tunable transconductance is employed to design filters. The filter constructed can be tuned in the range of few MHz. The proposed filter is operated using a 0.5V supply and its cutoff frequency can be easily adjusted. All circuits are designed and analyzed using a triple well 0.13μm CMOS process. This OTA is further modified to achieve better performance, in order to implement it in a complex filter. In low IF devices the down-conversion of image signal along with the wanted signal at the same frequency is a major problem. Complex filter can easily remove this image signal by applying a frequency shifting operation. A sixth order complex filter by implementing Leapfrog technique is designed using the differential OTA. The filter is designed to meet the Bluetooth and Zigbee standard requirements. The filter operates on a 0.5V supply voltage, and has very good results for Image rejection, sensitivity, noise and the filter is orthogonally tunable. The performance of the filter has been evaluated through simulation results by employing a triple well 0.13μm CMOS process. This filter design can be implemented in the Bluetooth devices used for the biomedical applications. / Η βιομηχανία της ηλεκτρονικής έχει αναπτυχθεί απίστευτα τα τελευταία χρόνια και η ανάπτυξη αυτή συνδυάζεται με την ανάγκη για συσκευές που λειτουργούν σε χαμηλή τάση και με χαμηλή κατανάλωση ενέργειας. Σε ότι αφορά την εμπορική τιμή, μια μικρή αύξηση της διάρκειας ζωής της μπαταρίας μπορεί να αντανακλάται σε μια αύξηση κατά μία τάξη μεγέθους της τιμής. Όλες οι εφαρμογές, από τις συσκευές πολυμέσων (όπως κινητά τηλέφωνα, φορητούς υπολογιστές, notebook κ.λπ.) έως και τις βιοϊατρικές συσκευές έχουν δει μια ταχεία πρόοδο. Όλες αυτές οι συσκευές, για να συνδέονται με ασύρματα δίκτυα, χρειάζονται πομποδέκτη χαμηλής τάσης και χαμηλής κατανάλωσης ισχύος. Η παρούσα διδακτορική διατριβή επικεντρώνεται στην ανάπτυξη νέων τεχνικών σχεδιασμού για ολοκληρωμένα κυκλώματα με έμφαση στα αναλογικά κυκλώματα, χαμηλής τάσης και χαμηλής ισχύος. Η συντριπτική πλειοψηφία των δομικών βαθμίδων αναλογικών κυκλωμάτων υψηλών επιδόσεων πραγματοποιείται σε τεχνολογία μετάλλου οξειδίου ημιαγωγού τρανζίστορ φαινομένου πεδίου (MOSFET) και εκμεταλλεύεται τα τρανζίστορ που παραδοσιακά λειτουργούν σε κόρο. Ωστόσο, υπάρχει η περιοχή ασθενούς αναστροφής, η οποία αφέθηκε ανεκμετάλλευτη μέχρι πρόσφατα, όπου η συμπεριφορά των τρανζίστορ MOS είναι παρόμοια με αυτήν των διπολικών τρανζίστορ. Αυτή η περιοχή θα μπορούσε να αξιοποιηθεί για τις συσκευές που απαιτούν λειτουργία με χαμηλή τάση τροφοδοσίας. Αντί να λειτουργούν στην περιοχή κόρου, τα τρανζίστορ MOS που χρησιμοποιούνται σε αυτό το σχεδιασμό, λειτουργούν σε ασθενή αναστροφή. Τα τρανζίστορ MOS στα προτεινόμενα κυκλώματα είναι ελεγχόμενα από το υπόστρωμα (bulk-driven). Στο συμβατικό τρόπο οδήγησης το υπόστρωμα παραμένει αχρησιμοποίητο και συνδέεται με την χαμηλότερη τάση τροφοδοσίας ή τη γείωση, ενώ η πύλη συνήθως, επιλέγεται για την εισαγωγή σήματος εισόδου και οδηγεί το κύκλωμα. Το υπόστρωμα μπορεί να χρησιμοποιηθεί ως είσοδος για το σήμα, μπορεί να μειώσει την τάση κατωφλίου (threshold voltage) των τρανζίστορ, και τελικά, χαμηλώνει την τάση λειτουργίας του τρανζίστορ. Σε αυτήν την διδακτορική διατριβή χρησιμοποιείται ως διαγωγός (transconductor) ένα τροποποιημένο κύκλωμα Nauta, ο οποίος λειτουργεί σε πολύ χαμηλές τάσεις. Οι ελεγχόμενοι διαγωγοί χρησιμοποιούνται για το σχεδιασμό των προτεινόμενων συντονιζόμενων φίλτρων. Τα κατασκευασμένα φίλτρα μπορούν να συντονιστούν στην περιοχή των λίγων MHz. Τα προτεινόμενα φίλτρα λειτουργούν χρησιμοποιώντας τάση τροφοδοσίας 0.5V και η συχνότητα αποκοπής τους μπορεί εύκολα να προσαρμοστεί. Όλα τα κυκλώματα σχεδιάζονται και εξομοιώνονται χρησιμοποιώντας μία τεχνολογία CMOS triple well 0.13μm. Ο υπό μελέτη τελεστικός ενισχυτής διαγωγιμότητας (Operational Transconductor Amplifier - OTA) έχει τροποποιηθεί περαιτέρω, για να επιτευχθεί καλύτερη απόδοση και να εφαρμοστεί σε ένα μιγαδικό φίλτρο. Η μετατροπή σήματος από τις μεσαίες συχνότητες (IF) στις χαμηλές συχνότητες παρουσιάζεται ένα σημαντικό πρόβλημα όπου μαζί με το επιθυμητό σήμα εμφανίζεται και το σήμα εικόνας στην ίδια συχνότητα. Τα μιγαδικά (complex) φίλτρα μπορούν να αφαιρέσουν εύκολα το σήμα εικόνας, εφαρμόζοντας μια διαδικασία μετατόπισης συχνότητας. Ένα μιγαδικό Leapfrog φίλτρο έχει σχεδιαστεί χρησιμοποιώντας διαφορικούς ενισχυτές διαγωγιμότητας. Το τελικό μιγαδικό φίλτρο δωδέκατης τάξης έχει σχεδιαστεί για να καλύψει τις απαιτήσεις του προτύπου Bluetooth και Zigbee. Το φίλτρο λειτουργεί με τάση τροφοδοσίας 0.5V και έχει πολύ καλά αποτελέσματα στην απόρριψη εικόνας, την ευαισθησία και το θόρυβο. Επίσης, η κεντρική συχνότητα και το εύρος συχνοτήτων είναι ανεξάρτητα ρυθμιζόμενα. Η απόδοση του φίλτρου έχει επαληθευτεί μέσω προσομοίωσης χρησιμοποιώντας μοντέλα τρανζίστορ μιας τεχνολογίας CMOS triple well 0.13μm. Φίλτρα που σχεδιάζονται με την προτεινόμενη μέθοδο μπορούν να εφαρμοστούν σε συσκευές Bluetooth που χρησιμοποιούνται και σε βιοϊατρικές εφαρμογές.

The objective of this research is to develop and design front-end analog circuits for Capacitive Micromachined Ultrasound Transducers (CMUTs) and optical grating MEMS microphone. This work is motivated by the fact that with micro-scaling, MEMS sense capacitance gets smaller in a CMUT array element for intravascular ultrasound imaging, which has dimensions of 70um x 70um and sub pico-farad capacitance. Smaller sensors lead to a lower active-to-parasitic ratio and thus, degrads sensitivity. Area and power requirements are also very stringent, such as the case of intravascular catheter implementations with CMOS-First CMUT fabrication approach. In this implementation, capacitive feedback charge amplifier is an alternative approach to resistive feedback amplifiers. Capacitive feedback charge amplifier provides high sensitivity, small area, low distortion and saving power. This approach of charge amplifiers is also suitable in capacitive microphones where it provides low power and high sensitivity. Another approach to overcome capacitive detection challenges is to implement optical detection. In the case of biomimetic microphone structure, optical detection overcomes capacitive detection's thermal noise issues. Also with micro-scaling, optical detection overcomes the increased parasitics without any sensitivity degradation, unlike capacitive detection. For hearing aids, along with sensitivity, battery life is another challenge. We propose the use of 1-bit front-end sigma-delta ADC for overall improved hearing aid power efficiency. Front-end interface based on envelope detection and synchronous detection schemes have also been designed. These interface circuits consume currents in microampere range from a 1.5V battery. Circuit techniques are used for maximizing linear range and signal handling with low supplies. The entire front end signal processing with Vertical Cavity Surface Emitting Laser (VCSEL) drivers, photodiodes, filters and detectors is implemented on a single chip in 0.35um CMOS process.