La technologie CMOS a contribué au développement de l'industrie des semi-conducteurs. Cependant, au fur et à mesure que le noeud technologique est réduit, la technologie CMOS fait face à des défis importants liés à la dissipation dûe aux courants de fuite et aux effets du canal court. Pour résoudre ce problème, les chercheurs se sont intéressés à la spintronique ces dernières années, compte tenu de la possibilité de fabriquer des dispositifs de taille réduite et d'opérations de faible puissance. La jonction tunnel magnétique (MTJ) est l'un des dispositifs spintroniques les plus importants qui peut stocker des données binaires grâce à la Magnétorésistance à effet tunnel (TMR). En dehors des applications de mémoire non volatile, la MTJ peut également être utilisée pour combiner ou remplacer les circuits CMOS pour implémenter un circuit hybride, de façon à combiner une faible consommation d'énergie et des performances à grande vitesse. Cependant, le problème de la conversion fréquente de charge en spin dans un circuit hybride peut entraîner une importante consommation d'énergie, ce qui obère l'intérêt pour des circuits hybrides. Par conséquent, le concept ASL qui repose sur un pur courant de spin comme support de l'information est proposé pour limiter les conversions entre charge et spin, donc pour réduire la consommation d'énergie. La conception de circuits à base de dispositif ASL entraîne de nombreux défis liés à l'hétérogénéité qu'ils introduisent et à l'espace de conception étendu à explorer. Par conséquent, cette thèse se concentre sur l'écart entre les exigences d'application au niveau du système et la fabrication des nanodispositifs. Au niveau du dispositif, nous avons développé un modèle compact intégrant le STT, la TMR, les effets d'injection/accumulation de spin, le courant de breakdown des canaux et le délai de diffusion de spin. Validé par comparaison avec les résultats expérimentaux, ce modèle permet d'explorer les paramètres du dispositif liés à la fabrication, tels que les longueurs de canaux et les tailles de MTJ, et aide les concepteurs à éviter leur destruction. De plus, ce modèle, décrit avec Verilog-A sur Cadence et divisé en plusieurs blocs : injecteur, détecteur, canal et contact, permet une conception indépendante et une optimisation des circuits ASL qui facilitent la conception de circuits hiérarchiques et complexes. En outre, les expressions permettant le calcul de l'injection/accumulation de spin pour le dispositif ASL utilisé sont dérivées. Elles permettent de discuter des phénomènes expérimentaux observés sur les dispositifs ASL. Au niveau circuit, nous avons développé une méthodologie de conception de circuit/système, en tenant compte de la distribution des canaux, de l'interconnexion des portes et des différents rapports de courant d'injection provoqués par la diffusion de spin. Avec les spécifications et les contraintes du circuit/système, les fonctions booléennes du circuit sont synthétisées en fonction de la méthode de synthèse développée et des paramètres de niveau de fabrication : longueur des canaux, et tailles MTJ sont spécifiées. Basé sur cette méthodologie développée, les circuits combinatoires de base qui forment une bibliothèque de circuits sont conçus et évalués en utilisant le modèle compact développé. Au niveau du système, un circuit DCT, un circuit de convolution et un système Intel i7 sont évalués en explorant les problèmes d'interconnexion : la répartition de l'interconnexion entre les portes et le nombre de tampons inséré. Avec des paramètres théoriques, les résultats montrent que le circuit/système ASL peut surpasser le circuit/système basé sur CMOS. De plus, le pipeline du circuit basé sur ASL est discuté avec MTJ comme tampons insérés entre les étapes. La reconfigurabilité provoquée par les polarités/valeurs du courant d'injection et les états des terminaux de control des circuits ASL sont également discutés avec l'exploration reconfigurable des circuits logiques de base. / The CMOS technology has tremendously affected the development of the semi-conductor industry. However, as the technology node is scaled down, the CMOS technology faces significant challenges set by the leakage power and the short channel effects. To cope with this problem, researchers pay their attention to the spintronics in recent years, considering its possibilities to allow smaller size fabrication and lower power operations. The magnetic tunnel junction (MTJ) is one of the most important spintronic devices which can store binary data based on Tunnel MagnetoResistance (TMR) effect. Except for the non-volatile memory, MTJ can be also used to combine with or replace the CMOS circuits to implement a hybrid circuit, for the potential to achieve low power consumption and high speed performance. However, the problem of frequent spin-charge conversion in a hybrid circuit may cause large power consumption, which diminishes the advantage of the hybrid circuits. Therefore, the ASL concept which uses a pure spin current to transport the information is proposed for fewer charge-spin conversions, thus for less power consumption. The design of ASL device-based circuits leads to numerous challenges related to the heterogeneity they introduce and the large design space to explore. Hence, this thesis focus on filling the gap between application requirements at the system level and the device fabrication at the device level. In device level, we developed a compact model integrating the STT, the TMR, the spin injection/accumulation effects, the channel breakdown current and the spin diffusion delay. Validated by comparing with experimental results, this model allows exploring fabrication-related device parameters such as channel lengths and MTJ sizes and help designers to prevent from device damages. Moreover, programmed with Verilog-A on Cadence and divided into several blocks: injector, detector, channel and contact devices, this model allows the independent design and cross-layer optimization of ASL-based circuits, that eases the design of hierarchical, complex circuits. Furthermore, the spin injection/accumulation expressions for the used ASL device are derived, enabling to discuss the experimental phenomena of the ASL device. In circuit level, we developed a circuit/system design methodology, taking into account the channel distribution, the gate interconnection and the different injection current ratios caused by the spin diffusion. With circuit/system specifications and constraints, the boolean functions of a circuit are synthesized based on the developed synthesis method and fabrication-level parameters: channel lengths, MTJ sizes are specified. Based on this developed methodology, basic combinational circuits that form a circuit library are designed and evaluated by using the developed compact model. In system level, a DCT circuit, a convolution circuit and an Intel i7 system are evaluated exploring the interconnection issues: interconnection distribution between gates and inserted buffer count. With theoretical parameters, results show that ASL-based circuit/system can outperform CMOS-based circuit/system. Moreover, the pipelining schema of the ASL-based circuit is discussed with MTJ as latches inserted between stages. The reconfigurability caused by the injection current polarities/values and the control terminal states of ASL-based circuits are also discussed with the reconfigurable exploration of basic logic circuits.

This thesis was developed to investigate the current models of sustainable development and architectural working and design practice and process to respond to the challenges of the current era defined as the Information Age. This thesis proposes a new model of sustainable development aligned to architecture and the Information Age, and a new integrated systems-design methodology to support it. Buildings were defined by le Corbusier in 1927 as ‘machines for living in’1 on the premise that these buildings facilitated our day-to-day user experience. The role of architecture as a facilitator for a sustainable existence is therefore subject to continued investigation. While there has been an increasing interest in environmental issues and ‘green building’, built environments have consequently failed to effectively holistically integrate core sustainable development principles in architecture. When compared to the definition of sustainable development in the UN Brundlandt Report of 1987, further research into an architectural design methodology is required to enable and plan for the long-term success of our built environments for current and, importantly, future generations. The practices and production of architecture risk being limited to reactively monitoring the design and construction processes for fixed moments in time, usually after the problem has presented itself. This is representative of localised, yet much publicised trends involving quantifiable rating systems for building performance. This does not contribute to long-term sustainability of the architectural product, nor the core principle of sustainable development to adequately meet the needs of current and future generations. The gravitation towards these easily-followed, yet limited-in-scope checklist processes is symptomatic of concepts of sustainable development remaining too broad and fragmented to facilitate focused, industry-appropriate implementation and design. The digital and information-based revolution has arrived, and humankind has now progressed to the point where constant and pervasive access to information and communication in a world of connected systems has changed the way we live and work. This is occurring at an exponential rate within what have been termed ‘knowledge-based societies’. Furthermore, the influence of the Information Age continues to manifest itself in the built environment through advancement of concepts and initiatives such as Smart Cities, intelligent buildings, and the Internet of Things. However, architectural approach and its emphasis on the building as a finite product comes at the expense of a holistic and integrated systems approach, and therefore requires investigation towards a revised design methodology. This thesis will begin by investigating the concept of sustainable development from its original inception to existing interpretations, and will interrogate its continued significance as a decades-old concept to the Information Age. This will be undertaken on the basis that sustainable development primarily aligns itself to the needs of humankind (current and future generations) and as such remains timeless as a core concept. However, the criteria that define sustainable development require investigation based on: a) their suitability towards human need in the context of knowledge-based societies and the Information Age, as well as b) their appropriateness for focused implementation in the scope of the built environment. In this aim, newly proposed criteria will be assimilated into a revised model for sustainable development, from which a methodology for design is developed. This will address the nature of the architectural process towards the creation of sustainable building solutions as a function of a systems approach, rather than a product approach. An integrated systems-design methodology is proposed, promoting the evolution of sustainable development theory in architecture for greater applicability to the Information Age. This systems-design methodology proactively identifies criteria for solving a given problem and the development of alternative solutions, while the proposed revised model for sustainable development is integrated to achieve a holistic building solution based on a systems process. This is inclusive of product (systems solution) delivery into the operation phase. The designer and project information model therefore transition into ‘information custodian’ and repository for knowledge gathering and exchange respectively, to the benefit of current and future stakeholders. This is addressed through various stages in design development and implementation, which apply contextually-based requirements of proposed sustainable development criteria, while catering for aspects of future flexibility, user experience, and knowledge-based development. This methodology expects the design practitioner to apply multi-dimensional evaluation and assessment tools at their discretion, and accommodate changing project dynamics over its life cycle. This implementation will benefit from future research and the introduction of new technologies to aid the process. This may furthermore be affected by new regulatory policy and guidelines affecting architects and the built environment. / Thesis (PhD)--University of Pretoria, 2018. / Architecture / PhD / Unrestricted

The number of electric powered sub-systems in road-vehicles is increasing fast. This development is primarily driven by the new and improved functionality that can be implemented with electro-mechanical sub-systems, but it is also necessary for the transition to electric and hybrid-electric drive trains. An electromechanical sub-system can be implemented as a physically integrated mechatronic module: controller, power electronics, electric motor, transmission and sensors, all integrated into one component. A mechatronic module, spans, as all mechatronic systems, over several closely coupled engineering disciplines: mechanics, electronics, electro-mechanics, control theory and computer science. In order to design and optimize a mechatronic system it is therefore desirable to design the system within all domains concurrently. Optimizing each domain or component separately will not result in the optimal system design. Furthermore, the very large production volumes of automotive sub-systems increase the freedom in the mechatronics design process. Instead of being limited to the selection from off-the shelf components, application specific components may be designed. The research presented in this thesis aims at development of an integrated design and optimization methodology for mechatronic modules. The target of the methodology is the conceptual design phase, where the number of design parameters is relatively small. So far, the focus has been on design methods for the electric motor and gearhead, two of the most important components in an actuation module. The thesis presents two methods for design and optimization of motor and gearhead in mechatronic applications. One discrete method, intended for the selection of off-the-shelf components, and one method mainly intended for high volume applications where new application specific components may be designed. Both methods can handle any type of load combination, which is important in mechatronic systems, where the load seldom can be classified as pure inertial or constant speed. Furthermore, design models relating spur gear weight, size and inertia to output torque and gear ratio are presented. It is shown that a gearhead has significantly lower inertia and weight than a motor. The results indicate that it almost always is favorable from a weight and size perspective to use a gearhead. A direct drive configuration may only be lighter for very high speed applications. The main contribution of this thesis is however the motor/gear ratio sizing methods that can be applied to any electromechanical actuation system that requires rotational motion. / QC 20101220

This thesis aimed to investigate ways to conduct participatory research practices that would gain knowledge of participants' relationships and experiences with/in their physical home environment by using a design probe. Through the probe, a new approach to participatory design research was formulated. This approach gives agency to participants through elements of auto-ethnography, thus shifting the traditional power structures that often exist between participants and designers. This new type of research could yield greater intimacy and mutuality between designers and their participants. Due to this, it has the potential to be meaningful when designing for the home environment, and therefore can be used for research and design within the Internet of Things.

Une plateforme de conception est une solution totale qui permet à une équipe de conception de développer un système sur puce. Une telle plateforme se compose d'un ensemble de bibliothèques et de circuits réutilisables (IPs), d'outils de CAO et de kits de conception en conformité avec les flots de conception et les méthodologies supportés. Les spécifications de ce type de plateforme offrent un large éventail d'informations, depuis des paramètres de technologie, jusqu'aux informations sur les outils. En outre, les développeurs de bibliothèque/IP ont des difficultés à obtenir les données nécessaires à partir ces spécifications en raison de leur informalité et complexité. Dans cette thèse, nous proposons des méthodologies, des flots et des outils pour formaliser les spécifications d'une plateforme de conception et les traiter. Cette description proposée vise à être utilisée comme une référence pour générer et valider les bibliothèques et les IPs. Nous proposons un langage de spécification basé sur XML (nommé LDSpecX). De plus, nous présentons une méthode basée sur des références pour créer une spécification fiable en LDSpecX et des mots-clés basés sur des tâches pour en extraire les données efficacement. A l'aide des solutions proposées, nous développons une plateforme de spécification. Nous développons une bibliothèque de cellules standard en utilisant cette plateforme de spécification. Nous montrons ainsi que notre approche permet de créer une spécification complète et cohérente avec une réduction considérable du temps. Cette proposition comble également l'écart entre les spécifications et le système automatique existant pour le développement rapide de bibliothèques/IPs. / A design platform (DP) is a total solution to build a System-On-Chip (SOC). DP consists of a set of libraries/IPs, CAD tools and design kits in conformity with the supported design flows and methodologies. The DP specifications provide a wide range of information from technology parameters like Process-Voltage-Temperature (PVT) corners to CAD tools’ information for library/IP development. However, the library/IP developers have difficulties in obtaining the desired data from the existing specifications due to their informality and complexity. In this thesis, we propose methodologies, flows and tools to formalize the DP specifications for their unification and to deal with it. The proposed description is targeting to be used as a reference to generate and validate libraries (standard cells, I/O, memory) as well as complex IPs (PLL, Serdes, etc.). First, we build a suitable data model to represent all required information for library/IP development and then propose a specification language named Library Development Specification based on XML (LDSpecX). Furthermore, we introduce a reference-based method to create a reliable specification in LDSpecX and task-based keywords to efficiently extract data from it. On the basis of the proposed solutions, we develop a specification platform. Experimentally, we develop a standard cell library from the specification creation to library validation by using the specification platform. We show that our approach enables to create a complete and consistent specification with a considerable reduction in time. It also bridges the gap between the specification and current automatic system for rapid library/IP development.

Cette thèse s’inscrit dans le contexte des systèmes embarqués qui sont qualifiés de complexes car leur développement nécessite une expertise pluridisciplinaire. Une stratégie de développement s'avère incontournable pour concevoir ces systèmes. Cette complexité est encore plus sévère dans le domaine du développement des systèmes embarqués pour UAV.Nous proposons une approche de développement orientés systèmes embarqués basés COTS. Cette démarche combine plusieurs méthodes issues du génie logiciel classique que nous avons adapté aux systèmes embarqués. Nous avons appliqué cette approche pour développer un système de capteurs embarqués pour un micro-UAV à voilures fixes.Le système embarqué développé a été déployé sur un robot classique, une bicyclette et un modèle réduit d'avion. L'objectif est de valider la consistance des données capteurs, compte tenu de la disparité des dynamiques entres ces systèmes. Ces expériences ont permis de mettre en évidence des similitudes théoriques entre ces 3 dynamiques. L'objectif est de pouvoir valider des systèmes embarqués pour UAV sur des plateformes à moindre coût et à moindre complexité, tout en garantissant la consistance des données capteurs et leur interprétation par rapport aux trois plateformes. Nous avons construit, aussi, une plateforme de simulation dont l’objectif est de supporter l’approche de développement proposée. Nous avons utilisé cette plateforme pour concevoir un système de contrôle, guidage et navigation pour un UAV à voilures fixes. Ces applications montrent, ainsi, l’efficacité de l’approche de développement proposée. / This thesis tackles the problem of embedded system design, which are often qualified as complex systems because their development requires multidisciplinary expertise. A development strategy is then essential to design these systems. As an application, we focused on UAV embedded systems, which show very severe development constraints.We propose a development approach oriented COTS-based embedded systems. This approach combines several methods from classic software engineering filed that we have adapted for embedded systems. We applied this approach to develop an embedded sensors system for a micro fixed wings UAVs.The designed embedded system has been deployed on an UAV, a mobile and a bicycle. The aim is to validate the UAV embedded system using a lower cost platforms and with less complexity, while ensuring sensors data consistency and interpretation regarding the dynamic of the three platforms. These experiments highlight the theoretical similarities between those three dynamics. Furthermore, we built a simulation platform that aims to support the proposed development approach. We used this platform to design a control, guidance and navigation system for a fixed wings UAV. These applications show the effectiveness of the proposed development approach.

Dans le domaine de la détection et du suivi d'obstacles pour les systèmes ADAS (Advanced Driver Assistance System) basés vision, il est nécessaire d'assurer la localisation à court terme du véhicule. Le SLAM (Simultaneous Localization and Mapping) basé vision propose de résoudre ce problème en combinant l’estimation de l’état du véhicule (pose dans un repère local et vitesses) et une modélisation incrémentale de l’environnement. Ce dernier est perçu par l'extraction de caractéristiques locales (points d'intérêt) dans une séquence d'images et leur suivi au cours du temps pour permettre la construction incrémentale d'une carte d'amers. Cette tâche de perception engendre une importante charge de calcul qui affecte très significativement la latence et la cadence du système. Les méthodologies de co-design permettent de concevoir une architecture mixte de calcul pour l“exécution d'une application particulière. Dans ce type d'architecture, l'utilisation d'accélérateurs matériels permet d'améliorer significativement les performances (temps d'exécution, encombrement, consommation). Le ZynQ (Xilinx) propose une architecture de prototypage mixte comprenant un processeur dual-core associé à des ressources matérielles configurables. L'objectif de cette thèse est donc de proposer une implémentation co-design d'un SLAM basé vision par la conception d'accélérateurs pour les opérations de vision afin de satisfaire les contraintes en performances des systèmes ADAS embarqués. La première contribution des travaux est la conception de cette chaîne complète 3D EKF-SLAM à l'aide une approche co-design. Nous avons défini et validé, selon notre méthodologie de conception, le choix d'une architecture Hardware-in-theloop (HIL) afin de valider les différentes itérations de conception. La seconde contribution est l'intégration de modules matériels dédiés pour accélérer les traitements de perception visuelle de cette chaîne (détection, description et mise en correspondance de points d’intérêt). / In the field of obstacle detection and tracking for vision-based ADAS (Advanced Driver Assistance System), it is necessary to perform short-term vehicle localisation. Vision based SLAM (Simultaneous Localization and Mapping) solves this problem by combining the vehicle state estimation (local pose and speeds) and an incremental modelling of the environment. The environment is perceived by extracting features (interest points) in a sequence of images and tracking them over time to allow an incremental landmarks map construction. The perception step leads to an important computational load which affects very significantly the system latency and throughput. Co-design methodologies allow to design a mixed processing architecture optimized for a specific application In this type of architecture, the use of hardware accelerators allows for great performance increase (throughput, memory size, power consumption). The ZynQ (Xilinx) provides a prototyping mixed-architecture including a dual-core microprocessor combined with configurable hardware resources. The goal of this thesis is to propose a co-design implementation of a vision-based SLAM processing chain involving hardware accelerators for image processing in order to meet the constraints of an embedded ADAS system. The first contribution is the design of a complete 3D EKF-SLAM processing chain thanks to a codesign approach. We defined and validated, according to the followed co-design approach, the choice of a Hardware-in-the-loop (HIL) architecture to validate the different design iterations. The second contribution is the integration of dedicated hardware modules to accelerate the visual perception computations of this processing chain (features detection, description and matching).

Tato práce popisuje navrženou metodologii pro návrh systémů odolných proti poruchám v FPGA schopnou ochránit systém před projevy přechodných a trvalých poruch. Oprava přechodné poruchy je prováděna částečnou dynamickou rekonfigurací. Oprava omezeného počtu trvalých poruch je založena na použití odolných architektur využívajících menší množství zdrojů než předchozí použitá architektura. Vadná část FPGA tak není dále využívána. Tato technika je založena na použití předkompilovaných konfigurací uložených v externí paměti. Pro snížení paměťových nároků pro uložení konfiguračních bitových posloupností je použita technika relokace.

This is a documentation of a programmatic design approach, moving through different levels of an established practice of grassroots activism. The text frames an open-ended, exploratory methodology, as four stages of investigation, trying to find possible ways to shape and increase understanding of, and facilitate a process, of co-designing a practice. It presents the experience of looking for opportunities for counter-narration, as contribution to an activist cause, and questioning the role, purpose and approach of a designer in a grassroots activist environment.

High Level Synthesis (HLS) is a methodology to translate a model developed in a high abstraction layer, e.g. C/C++/SystemC, that describes the algorithm into a Register-Transfer level (RTL) description like Verilog or VHDL. The resulting RTL description from the translation is subject to multiple user-controlled directives and an internal design space exploration algorithm specific to the toolchain used. HLS allow designers to focus on the behaviour of the design at a higher abstraction compared to the behavioural modelling available within the Hardware Description Language (HDL) as the compiler decides the movement of data and timing in the resulting design. Ericsson uses a legacy Advanced Peripheral Bus (APB) like interface called Memory/Register Interface (MIRI) interface for data movement in a subsystem of one of their Application-Specific Integrated Circuit (ASIC). The thesis attempts to upgrade the protocol to the more performant ARM Advanced Microcontroller Bus Architecture (AMBA) protocols’ Advanced High-performance Bus (AHB) or Advanced eXtensible Interface (AXI) interfaces. SystemC provides a host of functionalities to define the complete behaviour of the circuit at a high level of abstraction. This thesis will explore the effect of the structuring SystemC models on their synthesis, and perform design space exploration to understand the best design methodology to adopt in a SystemC model design and compare the models based on the final synthesis metrics like area, timing, and register counts. The toolchain for the thesis will be the Stratus HLS compiler developed by Cadence. Stratus supports all synthesizable constructs of SystemC. Most HLS research focuses on improving Design Space Exploration algorithms used internally in the HLS tools. However, designers can utilize algorithm structuring to provide the HLS engines with a better starting point. In this thesis, the Stratus toolchain will be used to experiment with different models with equivalent behaviour and performance. Thereafter, extract which constructs used in the models are optimal for allowing the internal design space exploration algorithm to perform in the best way possible. / HLS är en metod för att översätta en modell utvecklad på hög abstraktionsnivå t.ex. C/C++/SystemC som beskriver algoritmen på registeröverföringsnivå (RTL) som Verilog eller VHDL. Den resulterande RTL-beskrivningen utsätts för flera användarkontrollerade direktiv och en intern Design Space Exploration (DSE) algoritm, vilken är specifik för den verktygskedja som används. Detta gör det möjligt för en designer att fokusera på konstruktion beteende på en högre abstraktionsnivå jämfört med den beteendemodellering som finns tillgänglig inom det hårdvarubeskrivande språket (HDL:en) när kompilatorn bestämmer tidpunkten för utbytet av data i den resulterande designen. Ericsson använder ett äldre gränssnitt för Advanced Peripheral Bus (APB) som kallas Memory/Register Interface (MIRI), vilket är ett gränssnitt för utbyte av data i ett delsystem i en av deras Application-Specific Integrated Circuit (ASIC:ar). Avhandlingen försöker uppgradera protokollet till ett av de det mer högpresterande ARM Advanced Microcontroller Bus Architecture – protokollen Advanced High-Performance Bus (AHB) eller Advanced eXtensible Interface (AXI). SystemC tillhandahåller en mängd funktioner för att definiera kretsens fullständiga beteende vid en hög abstraktionsnivå. Denna avhandling utforskar effekten av strukturerade SystemC-modeller och deras syntesresultat samt konstruktionsrymden, för att förstå den bästa designmetodiken i ett SystemC-modelleringsdesignflöde och jämföra modellerna baserade på de slutliga syntesmätvärdena som storlek, timing, etc. Verktygskedjan för avhandlingen kommer att vara Stratus HLS -kompilatorn som utvecklats av Cadence. Stratus stöder alla syntetiserbara konstruktioner av SystemC. HLS-forskningen fokuserar främst på att förbättra Design Space Exploration, dvs de algoritmer som används internt i HLS-verktygen för att komma fram till lösningar. För att ge HLS -motorerna en bättre utgångspunkt. I denna avhandling kommer Stratus att användas för att utvärdera olika modeller med ekvivalent beteende och nästan samma prestanda efter Syntes, för att komma fram till vilka konstruktioner är optimala för att den interna DSE-algoritmen skall fungera bäst.