The primary objectives in this research are to develop computer-aided design (CAD) tools for Design for Manufacturability (DFM) solutions that enable designers to conduct more rapid and more accurate systematic variation analysis, with different design enhancement techniques. Four main CAD tools are developed throughout my thesis. The first CAD tool facilitates a quantitative study of the impact of systematic variations for different circuits' electrical and geometrical behavior. This is accomplished by automatically performing an extensive analysis of different process variations (lithography and stress) and their dependency on the design context. Such a tool helps to explore and evaluate the systematic variation impact on any type of design. Secondly, solutions in the industry focus on the "design and then fix philosophy", or "fix during design philosophy", whereas the next CAD tool involves the "fix before design philosophy". Here, the standard cell library is characterized in different design contexts, different resolution enhancement techniques, and different process conditions, generating a fully DFM-aware standard cell library using a newly developed methodology that dramatically reduce the required number of silicon simulations. Several experiments are conducted on 65nm and 45nm designs, and demonstrate more robust and manufacturable designs that can be implemented by using the DFM-aware standard cell library. Thirdly, a novel electrical-aware hotspot detection solution is developed by using a device parameter-based matching technique since the state-of-the-art hotspot detection solutions are all geometrical based. This CAD tool proposes a new philosophy by detecting yield limiters, also known as hotspots, through the model parameters of the device, presented in the SPICE netlist. This novel hotspot detection methodology is tested and delivers extraordinary fast and accurate results. Finally, the existing DFM solutions, mainly address the digital designs. Process variations play an increasingly important role in the success of analog circuits. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. The fourth CAD solution, proposed in this thesis, introduces a variability-aware DFM solution that detects, analyze, and automatically correct hotspots for analog circuits.

The primary objectives in this research are to develop computer-aided design (CAD) tools for Design for Manufacturability (DFM) solutions that enable designers to conduct more rapid and more accurate systematic variation analysis, with different design enhancement techniques. Four main CAD tools are developed throughout my thesis. The first CAD tool facilitates a quantitative study of the impact of systematic variations for different circuits' electrical and geometrical behavior. This is accomplished by automatically performing an extensive analysis of different process variations (lithography and stress) and their dependency on the design context. Such a tool helps to explore and evaluate the systematic variation impact on any type of design. Secondly, solutions in the industry focus on the "design and then fix philosophy", or "fix during design philosophy", whereas the next CAD tool involves the "fix before design philosophy". Here, the standard cell library is characterized in different design contexts, different resolution enhancement techniques, and different process conditions, generating a fully DFM-aware standard cell library using a newly developed methodology that dramatically reduce the required number of silicon simulations. Several experiments are conducted on 65nm and 45nm designs, and demonstrate more robust and manufacturable designs that can be implemented by using the DFM-aware standard cell library. Thirdly, a novel electrical-aware hotspot detection solution is developed by using a device parameter-based matching technique since the state-of-the-art hotspot detection solutions are all geometrical based. This CAD tool proposes a new philosophy by detecting yield limiters, also known as hotspots, through the model parameters of the device, presented in the SPICE netlist. This novel hotspot detection methodology is tested and delivers extraordinary fast and accurate results. Finally, the existing DFM solutions, mainly address the digital designs. Process variations play an increasingly important role in the success of analog circuits. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. The fourth CAD solution, proposed in this thesis, introduces a variability-aware DFM solution that detects, analyze, and automatically correct hotspots for analog circuits.

Much of today's high performance computing engines and hand-held mobile devices are products of aggressive CMOS scaling. Technology scaling in semiconductor industry is mainly driven by corresponding improvements in optical lithography technology. Photolithography, the art used to create patterns on the wafer is at the heart of the semiconductor manufacturing process. Lately, improvements in optical technology have been difficult and slow. The transition to deep ultra-violet (DUV) light source (193nm) required changes in lens materials, mask blanks, light source and photoresist. It took more than ten years to develop a stable chemically amplified resist (CAR) for DUV. Consequently, as the industry moves towards manufacturing end-of-the-roadmap CMOS devices, lithography is still based on 193nm light source to print critical dimensions of 45nm, 32nm and likely 22nm. Sub-wavelength lithography creates a number of printability issues. The printed patterns are highly sensitive to topographic changes due to metal planarization, overlay errors, focus and dose variations, random particle defects to name a few. Design for Manufacturability methodologies came into being to help analyze and mitigate manufacturing impacts on the design. Although techniques such as Resolution Enhancement Techniques (RET) which involve optical proximity correction (OPC), phase shift masking (PSM), off-axis illumination (OAI) have been used to greatly improve the printability and better the manufacturing process window, they cannot perfectly compensate for these lithographic deficiencies. DFM methods were primarily devised to predict and correct systematic patterning problems that arise during manufacturing. Apart from systematic errors, random manufacturing variations may occur during photolithography. This is where a statistical approach to modeling of error behavior and its impact on different design parameters may prove to be effective. By incorporating statistical analysis to parameter variation, an effective, non-conservative design can be obtained. IC manufacturing yield is the foremost measure that determines the profitability of a given semiconductor manufacturing process. Thus early prediction of yield detractors is an important step in the design process. Such predictions are based on models, which in turn are rooted in manufacturing process. Success of yield prediction is based on quality of models. The models must capture physical phenomena and yet be efficient for computation. In this work, we present a lithography-based yield model that is computationally practical for use in the design process. The work also provides a methodology to perform statistical lithography rules check to identify hot spots in the design that can contribute to yield loss. Yield recovery methods aimed at minimally modifying the design ultimately produce more printable masks. Apart from IC manufacturing yield, ICs today are vulnerable to various reliability failures including electromigration (EM), negative bias temperature instability (NBTI), hot carrier injection (HCI) and electro-static discharge (ESD). Though such reliability issues have been examined since the beginning of CMOS, manufacturability impacts have created a renewed interest in analyzing them. In this dissertation, we introduce the concept of Design for reliable manufacturability (DFRM) to consider the effect of linewidth changes, gate oxide thickness variations and other manufacturing artifacts. A novel Litho-aware EM calibration and analysis has bee shown in this work. Results indicate that there is a significant difference in EM estimation when litho-predicted layouts are considered during analysis. DFM has always looked at linewidth and material thickness variation as detractors to the design. However, such variations are inevitable. In this work we also consider modeling sensitivity to variations to improve test pattern quality. Test structures sprinkled all over the wafer encounter varying process fluctuations. This can be harnessed to predict the current lithographic process corner which will later be used to choose the test pattern set that results in maximum fault coverage. In summary, the objective of this dissertation is to consider the impact of sub-wavelength lithography on printability and the overall impact on circuit reliability and manufacturing test development.

The emergence of multi-band communications standards, and the fast pace of the consumer electronics markets for wireless/cellular applications emphasize the need for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated. For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits become the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level sizing technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework. In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for RF circuits for SOP-based wireless applications. The proposed statistical analysis framework is based on layout segmentation, lumped element modeling, sensitivity analysis, and extraction of probability density functions using convolution methods. The statistical analysis takes into account the effect of thermo-mechanical stress and process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability functions and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.

As the semiconductor technology roadmap further extends, the development of next generation silicon systems becomes critically challenged. On the one hand, design and manufacturing closures become much more difficult due to the widening gap between the increasing integration density and the limited manufacturing capability. As a result, manufacturability issues become more and more critically challenged in the design of reliable silicon systems. On the other hand, the continuous scaling of feature size imposes critical issues on traditional interconnect materials (Cu/Low-K dielectrics) due to power, delay and bandwidth concerns. As a result, multiple classes of new materials are under research and development for future generation technologies. In this dissertation, we investigate several critical Computer-Aided Design (CAD) challenges under advanced nanolithography and nanophotonics technologies. In addressing these challenges, we propose systematic CAD methodologies and optimization techniques to assist the design of high-yield and high-performance integrated circuits (IC) with low power consumption. In Very Large Scale Integration (VLSI) CAD for nanolithography, we study the manufacturing variability under resolution enhancement techniques (RETs) and explore two important topics: (1) fast and high fidelity lithography hotspot detection; (2) generic and efficient manufacturability aware physical design. For the first topic, we propose a number of CAD optimization and integration techniques to achieve the following goals in detecting lithography hotspots: (a) high hotspot detection accuracy; (b) low false-positive rate (hotspot false-alarms); (c) good capability to trade-off between detection accuracy and false-alarms; (d) fast CPU run-time; and (e) excellent layout coverage and computation scalability as design gets more complex. For the second topic, we explore the routing stage by incorporating post-RET manufacturability models into the mathematical formulation of a detailed router to achieve: (a) significantly reduced lithography-unfriendly patterns; (b) small CPU run-time overhead; and (c) formulation generality and compatibility to all types of RETs and evoling manufacturing conditions. In VLSI CAD for nanophotonics, we focus on three topics: (1) characterization and evaluation of standard on-chip nanophotonics devices; (2) low power planar routing for on-chip opto-electrically interconnected systems; (3) power-efficient and thermal-reliable design of nanophotonics Wavelength Division Multiplexing for ultra-high bandwidth on-chip communication. With simulations and experiments, we demonstrate the critical role and effectiveness of Computer-Aided Design techniques as the semiconductor industry marches forward in the deeper sub-micron (45nm and below) domain. / text

Intensive competition on the global market puts great pressure on manufacturing companies to develop and produce products that meet requirements from customers and investors. One key factor in meeting these requirements is the efficiency of the product development and the production preparation processes. Design automation is a powerful tool to increase efficiency in these two processes. The benefits of automating the manufacturability analysis process, a part of the production preparation process, are shortened lead-time, improved product performance, quality assurance, and, ultimately, decreased costs. Further, automation is beneficial as it increases the ability to adapt products to new product specifications with production preparations done in a few or in a single step. During the automation process, knowledge about the manufacturability analysis process is collected and stored in central systems, thus allowing full control over the design of production equipments. Topics addressed in this thesis include the flexibility of design automation systems, knowledge-bases containing alternative design rules, the automation of the finite element analysis process, manufacturability analysis over several productions steps, and the determination of production limits by looping the automated manufacturability analysis process. These topics are discussed in connection with the rotary draw bending of aluminum profiles. It is concluded that the concept of design automation can be applied to the manufacturability analysis process at different levels of automation depending on the characteristics of the implemented knowledge. The concept of object orientation should be adapted when implementing a knowledge-base and when developing the geometrical representations of the products. This makes a design automation system flexible enough to edit underlying knowledge and to extend the targeted design space. It is possible to automate the process of setting up, running, and interpreting finite element analyses to a great extent, enabling the design automation system to evaluate its own design proposals. It is also possible to enable such systems to consider sequences of manufacturing steps and loop them to develop decision support guiding engineers early in the design process, saving time and money while still assuring high product quality.

Additive Manufacturing (AM) using the Powder Bed Fusion (PBF) is a relatively new manufacturing method that is capable of creating shapes that was previously practically impossible to manufacture. Many think it will revolutionize how manufacturing will be done in the future. This thesis is about some aspects of when and how to Design for Additive Manufacturing (DfAM) when using the PBF method in metal materials. Designing complex shapes is neither easy nor always needed, so when to design for AM is a question with different answers depending on industry or product. The cost versus performance is an important metric in making that selection. How to design for AM can be divided into how to improve performance and how to improve additive manufacturability where how to improve performance once depends on product, company and customer needs. Using advanced part shaping techniques like using Lattices or Topology Optimization (TO) to lower part mass may increase customer value in addition to lowering part cost due to faster part builds and less powder and energy use. Improving PBF manufacturability is then warranted for parts that reach series production, where determining an optimal build direction is key as it affects many properties of PBF parts. Complex shapes which are designed for optimal performance are usually more sensitive to defects which might reduce the expected performance of the part. Non Destructive Evaluation (NDE) might be needed to certify a part for dimensional accuracy and internal defects prior use. The licentiate thesis covers some aspects of both when to DfAM and how to DfAM of products destined for series production. It uses design by Lattices and Topology Optimization to reduce mass and looks at the effect on part cost and mass. It also shows effects on geometry translation accuracies from design to AM caused by differences in geometric definitions. Finally it shows the effect on how different NDE methods are capable of detecting defects in additively manufactured parts.

Unmanned Air Vehicles (UAVs) have recently gained attention due to their increased ability to perform sophisticated missions with less cost and/or risk than their manned counterparts. This thesis develops approaches to the use of compliant mechanisms in the design of deployable wings for small UAVs. Although deployable wings with rigid-link mechanisms have been used in the past to maintain flight endurance while minimizing required storage volume, compliant mechanisms offer many advantages in manufacturability and potential space savings due to function sharing of components. A number of compliant, deployable wing concepts are generated and a classification system for them is formed. The pool of generated concepts serves as a basis for stimulating future concept ideas. A methodology is also proposed for evaluating concepts for a given application. The approach to developing compliant designs for certain applications is illustrated through two example designs, which demonstrate key portions of the proposed design process. Each is modeled and analyzed to demonstrate viability.