The following dissertation examines the history of general hospitals in modern, central and western Canada. It follows extensive case studies of the Toronto, Winnipeg, Calgary, and Vancouver general hospitals. The last few decades have seen an expanded interest in hospitals by Canadian medical historians, but the overall literature is thin. Further, many of the extant histories focus on a particular constituent: the medical profession, administrators, or architects. In this dissertation I argue that these general hospitals were contested spaces, and that their organization and layout reflected negotiation between several parties. A further important vector is the role hospitals played in the social life of their communities. As these general hospitals grew, and began treating middle-class patients, they also required large sums of money from the public purse. Administrators had to account for the shape and use of medical space to the general public that helped finance it, as they did to the doctors who worked there. During the period 1880-1945 general hospitals moved from the periphery of medical care to the centre, but not without substantial growing pains. These institutions routinely lacked funds and space, and remained in operation as much through the efforts of medical professionals as by concerned citizens. After the Second World War the Federal Government shifted from a standoffish institution to one ready to release funds and administrative energies towards new ideals of social welfare. Funding increased dramatically for the building of new hospitals, and legislative developments such as Medicare transformed the social and political relationship between hospitals and patients. / Thesis / Doctor of Philosophy (PhD) / This dissertation began with the question: why do our general hospitals look the way that they do? It goes on to examine the ways in which multiple actors, including many non-medical ones such as local citizens, city councils, architects, and patients, interfaced with administrators and doctors to establish and build general hospitals in four Canadian cities. The core argument is that these were contested spaces, which reflected the communities in which they existed.

Many microwave (RF) circuit designs require passive distributed sub-components with prescribed scattering parameters. These sub-components have typically been realised by cascading building-block configurations (eg. transmission lines of specific lengths, bends in transmission lines, coupled lines, and so on) of standard shape, and then adjusting the dimensions of selected prescribed features of these building-blocks. The problem with this approach is that the resulting sub-component may take up more "real-estate" on the overall circuit board than can be tolerated, may require tolerances that are too tight and hence be more costly than product developers can allow, can lead to less-than-best performance because we select the building-blocks (that we think are needed) ahead of time, and so on. The research in this thesis contributes to the shape synthesis approach of physical microstrip circuit design. The shape synthesis process is usually contrasted to traditional design by recognizing that it does not merely adjust the dimensions of a set of prescribed geometrical features on pre-selected shapes, but allows the electromagnetic physics to tell us what the sub-component layout needs to be (and it can be unconventional) in order to obtain the required performance. Existing shape synthesis techniques are based on the discrete- or continuous-pixelation method. Each of these approaches, however, have disadvantages (eg. too many degrees of freedom required to achieve the geometrical resolution necessary; the need for arbitrary decisions to fix material properties) that have prevented shape synthesis from being accepted for widespread use in design practice. In this thesis we develop, implement and apply a completely new shape synthesis approach, called the subtractive approach, that overcomes many of the above-mentioned disadvantages of pixelation-based methods It reduces the number of variables (degrees of freedom) needed in spite of the fact that the "design space" is significantly broadened by this approach. The latter is confirmed by the fact that it produces physical circuit geometries that we would not have come up with using traditional design methods. Examples are provided of the application of the new subtractive shape synthesis method. This new method involves continuous variables directly related to the physical circuit geometry, and thus could be used with surrogate modelling, unlike some existing shape synthesis procedures.

With ever increasing contents (safety, driver assistance, infotainment, etc.) in today's automotive systems that rely on electronics and software, the supporting architecture is integrated by a complex set of heterogeneous data networks. A modern automobile contains up to 100 ECUs and several heterogeneous communication buses (such as CAN, FlexRay, etc.), exchanging thousands of signals. The automotive Original Equipment Manufacturers (OEMs) and suppliers face a number of challenges such as reliability, safety and cost to incorporate the growing functionalities in vehicles. Additionally, reliability, safety and cost are major concerns for the industry. One of the important challenges in automotive design is the efficient and reliable transmission of signals over communication networks such as CAN and CAN-FD. With the growing features in automotives, the OEMs already face the challenge of saturation of bus bandwidth hindering the reliability of communication and the inclusion of additional features. In this dissertation, we study the problem of optimization of bandwidth utilization (BU) over CAN-FD networks. Signals are transmitted over the CAN/CAN-FD bus in entities called frames. The signal-to-frame-packing has been studied in the literature and it is compared to the bin packing problem which is known to be NP-hard. By carefully optimizing signal-to-frame packing, the CAN-FD BU can be reduced. In Chapter 3, we propose a method for offset assignment to signals and show its importance in improving BU. One of our contributions for an industrial setting is a modest improvement in BU of about 2.3%. Even with this modest improvement, the architecture's lifetime could potentially be extended by several product cycles, which may translate to saving millions of dollars for the OEM. Therefore, the optimization of signal-to-frame packing in CAN-FD is the major focus of this dissertation. Another challenge addressed in this dissertation is the reliable mapping of a task model onto a given architecture, such that the end-to-end latency requirements are satisfied. This avoids costly redesign and redevelopment due to system design errors. / Ph. D. / Automobiles today are equipped with a variety of advanced features, such as adaptive cruise control, lane departure warning systems, information and entertainment systems, etc. These advanced features rely on electronics and software. A modern automobile consists of up to 100 computer systems that are interconnected by several buses (in-vehicle communication networks), exchanging thousands of signals (which are data entities such as sensor data, control commands, etc.). The addition of new functionalities means additional complexity and more demand of existing resources such as bus bandwidth. The automotive companies face a number of challenges such as reliability, safety and cost to incorporate the growing features in vehicles with the limited resources. In this dissertation, we study the problem of optimization of bandwidth utilization (BU) over a communication bus used in automotives. In Chapter 3, we show that for an automobile company even a modest improvement in BU of about 2.3% could potentially extend the bus architecture’s lifetime by several product cycles. This may translate to saving millions of dollars for the company. Therefore, the optimization of bandwidth utilization over a communication bus is the major focus of this dissertation. Another problem addressed in this dissertation is the reliable mapping of a software model onto a given architecture (for an automotive system), such that the timing requirements are satisfied. This avoids costly redesign and redevelopment due to system design errors.

Although high-level synthesis has been researched for many years, synthesizing minimum hardware implementations under a throughput constraint for computationally intensive algorithms remains a challenge. In this thesis, three important techniques are studied carefully and applied in an integrated way to meet this challenging synthesis requirement. The first is pipeline scheduling, which generates a pipelined schedule that meets the throughput requirement. The second is module selection, which decides the most appropriate circuit module for each operation. The third is resource sharing, which reuses a circuit module by sharing it between multiple operations. This work shows that combining module selection and resource sharing while performing pipeline scheduling can significantly reduce the hardware area, by either using slower, more area-efficient circuit modules or by time-multiplexing faster, larger circuit modules, while meeting the throughput constraint. The results of this work show that the combined approach can generate on average 43% smaller hardware than possible when a single technique (resource sharing or module selection) is applied. There are four major contributions of this work. First, given a fixed throughput constraint, it explores all feasible frequency and data introduction interval design points that meet this throughput constraint. This enlarged pipelining design space exploration results in superior hardware architectures than previous pipeline synthesis work because of the larger sapce. Second, the module selection algorithm in this work considers different module architectures, as well as different pipelining options for each architecture. This not only addresses the unique architecture of most FPGA circuit modules, it also performs retiming at the high-level synthesis level. Third, this work proposes a novel approach that integrates the three inter-related synthesis techniques of pipeline scheduling, module selection and resource sharing. To the author's best knowledge, this is the first attempt to do this. The integrated approach is able to identify more efficient hardware implementations than when only one or two of the three techniques are applied. Fourth, this work proposes and implements several algorithms that explore the combined pipeline scheduling, module selection and resource sharing design space, and identifies the most efficient hardware architecture under the synthesis constraint. These algorithms explore the combined design space in different ways which represents the trade off between algorithm execution time and the size of the explored design space.

When building aircrafts, structural components must be designed for high strength, low cost, and easy assembly.To meet these conditions structural components are often based upon previous designs, even if a new component is developed.Refining previous designs can be a good way of preserving knowledge but can also limit the exploration of new design concepts. Currently the design process for structural aircraft components at SAAB is managed by design engineers. The design engineer is responsible for ensuring the design meets requirements from several different disciplines such as structural analysis, manufacturing, tool design, and assembly.Therefore, the design engineer needs to have good communication with all disciplines and an effective flow of information. The previous design is refined, it is then reviewed and approved by adjacent disciplines.Reviewing designs is an iterative process, and when several disciplines are involved it quickly becomes time consuming.Any time the design is altered it has to be reviewed once more by all disciplines to ensure the change is acceptable.So there is a need for further customizing the design concept to decrease the number of iterations when reviewing. Design Space Exploration DSE is a well known method to explore design alternatives before implementation and is used to find new concepts.This thesis investigates if DSE can be used to facilitate the design process of structural aircraft components and if it can support the flow of information between different disciplines.To find a suitable discipline to connect with design a prestudy is conducted, investigating what information affect structural design and how it is managed.The information flow is concluded in a schematic diagram where structural analysis is chosen as additional discipline. By using topology optimization in a DSE, design and structural analysis are connected.The design space can be explored with regards to structural constraints.The thesis highlights the possibilities of using DSE with topology optimization for developing structural components and proposes a method for including it in the design process.

Hoje em dia, desenvolvedores de sistemas embarcados enfrentam uma crescente complexidade de projeto, tanto nas aplicações quanto nas plataformas usadas para executá-las. O uso de plataformas complexas faz com que os engenheiros precisem fazer escolhas não-triviais, e muitas vezes contra-intuitivas durante a fase de projeto. Para permitir que os projetistas gerenciem esta complexidade, o uso de metodologias baseadas em modelos tem atraído atenção, e dentro deste contexto, a metodologia HIPAO2 está sendo desenvolvida dentro da UFRGS. Dentre os problemas que os engenheiros precisam enfrentar, o mapeamento entre tarefas e processadores em sistemas multiprocessados heterogêneos é um problema NP-completo, onde o espaço de projeto rapidamente se torna grande demais para que seja explorado satisfatoriamente de maneira manual. Este trabalho detalha a extensão das ferramentas que suportam a metodologia HIPAO2, de maneira a incluir facilidades de Exploração de Espaço de Projeto semi-automática para a solução deste problema. A ferramenta proposta faz uso de um algoritmo genético multiobjetivo para evidenciar tradeoffs existentes no projeto, e algoritmos de análise de aplicações modeladas como synchronous dataflow para avaliar possíveis mapeamentos sem um custo computacional proibitivo. / Designers of today’s embedded systems are faced with increasing complexity both in the applications being developed and the platforms they run on. The use of complex platforms means that the engineers need to make non-trivial and many times non-intuitive decisions during the design phase. To help developers work with this complexity, model-driven techniques are gaining attention, and in this context, the HIPAO2 model-driven engineering methodology is being developed at UFRGS. Among the problems that designers must solve, the task-to-processor mapping in heterogeneous multiprocessor systems is an NP-complete problem and the design space will quickly become too large to be explored adequately by humans. This work details the extension of the tools that support HIPAO2 to include semiautomatic Design-Space Exploration capabilities for the mapping problem. The proposed tool includes the use of a multiobjective genetic algorithm to make tradeoffs explicit to the designers; it also uses synchronous dataflow analysis algorithms to evaluate potential alternatives with a reasonable computational cost.

Finite element analysis (FEA) software is used to obtain linear and non-linear solutions to one, two, and three-dimensional (3-D) geometric problems that will see a particular load and constraint case when put into service. Parametric FEA models are commonly used in iterative design processes in order to obtain an optimum model given a set of loads, constraints, objectives, and design parameters to vary. In some instances it is desirable for a designer to obtain some intuition about how changes in design parameters can affect the FEA solution of interest, before simply sending the model through the optimization loop. This could be accomplished by running the FEA on the parametric model for a set of part family members, but this can be very timeconsuming and only gives snapshots of the models real behavior. The purpose of this thesis is to investigate a method of visualizing the FEA solution of the parametric model as design parameters are changed in real-time by approximating the FEA solution using surrogate modeling methods. The tools this research will utilize are parametric FEA modeling, surrogate modeling methods, and visualization methods. A parametric FEA model can be developed that includes mesh morphing algorithms that allow the mesh to change parametrically along with the model geometry. This allows the surrogate models assigned to each individual node to use the nodal solution of multiple finite element analyses as regression points to approximate the FEA solution. The surrogate models can then be mapped to their respective geometric locations in real-time. Solution contours display the results of the FEA calculations and are updated in real-time as the parameters of the design model change.

Le chiffrement homomorphe est un système de cryptographie permettant la manipulation de données chiffrées. Cette propriété offre à un utilisateur la possibilité de déléguer des traitements sur ses données privées, à un tiers non fiable sur un serveur distant, sans perte de confidentialité.Bien que les recherches sur l'homomorphe soient, à ce jour, encore récentes, de nombreux schémas de chiffrement ont été mis au point. Néanmoins, ces schémas souffrent de quelques inconvénients, notamment, de temps d'exécution particulièrement longs et de coûts mémoire importants. Ces limitations rendent difficile la comparaison des schémas afin de déterminer lequel serait le plus adapté pour une application donnée, c’est-à-dire le moins coûteux en temps et en mémoire.Ce manuscrit présente PAnTHErS, un outil rassemblant plusieurs fonctionnalités permettant de répondre à la problématique citée ci-dessus. Dans l'outil PAnTHErS, les schémas de chiffrement homomorphe sont tout d'abord représentés dans un format commun grâce à une méthode de modélisation. Puis, une analyse théorique estime, dans le pire cas, la complexité algorithmique et le coût mémoire de ces schémas en fonction des paramètres d’entrée fournis. Enfin, une phase de calibration permet la conversion des analyses théoriques en résultats concrets : la complexité algorithmique est convertie en un temps d'exécution estimé en secondes et le coût mémoire en une consommation estimée en mébioctets.Toutes ces fonctionnalités associées ont permis la réalisation d’un module d'exploration qui, à partir d'une application, sélectionne les schémas ainsi que les paramètres d'entrée associés produisant des temps d'exécution et coûts mémoire proches de l'optimal. / Homomorphic encryption (HE) is a cryptographic system allowing to manipulate encrypted data. This property enables a user to delegate treatments on private data to an untrusted third person on a distant server, without loss of confidentiality.Even if current researches in HE domain are still young, numerous HE schemes have been created. Nevertheless, those schemes suffer from some drawbacks, especially, from too long execution times and important memory costs. These restrictions make difficult to compare schemes in order to define which one is the most appropriate for a given application, i. e. the less expensive in terms of time and memory.This thesis presents PAnTHErS, a tool gathering several features to answer to the previous problem. In the tool PAnTHErS, homomorphic encryption schemes are first represented into a common structure thanks to a modeling method. Then, a theoretical analysis evaluates, in the worst case, computational complexity and memory consumption of those schemes according to given input parameters. Finally, a calibration phase enables conversion of theoretical analysis into concrete results: computational complexity is converted into an estimated execution time in seconds and memory cost into an estimated consumption in mebibytes.These gathered features allowed the creation of an exploration method which, from an application, selects best schemes and associated input parameters that implies close to optimal execution times and memory costs.

This thesis critically reflects on co-operative design workshops that I have conducted. The basic method used in these workshops draws on the participants’ embodied knowing. In the over twenty workshops that are analysed here a wide range of participants have been involved: family members, employees, persons with disabilities, and other stakeholders like manufacturers, service providers and civil servants. The topics have varied, but they have mostly been related to ICT products and services. Most of the workshops were conducted within various research projects. In order to analyse this diverse range of workshops I use several different theories and concepts. I articulate and analyse the design aspects of the activities by using established design theories and concepts. The conceptual tool design space, meaning all possible design proposals, is used for understanding the design process. I also use theories from other fields in order to analyse three different aspects of the workshops: the participants’ activities, the designers’ responsibility, and the process. To analyse the way that the participants co-operatively create knowledge, theories of interpersonal actions are used; to analyse the work done by the designer/conductor, theories of frames are used; and to analyse the process, the theory of actualisation and realisation is used. During the workshops the participants co-operatively make scenarios, props and video prototypes in order to create proposals for desired interactions with future artefacts. Contributions include accounts of critical situations during the workshops and suggested strategies for dealing with them. Some implications are relevant to the design field in general, for example the importance of a process where the participants trust each other, learn from each other and work effectively with difficult issues by creating multiple proposals that facilitate understanding of the design space. I also offer arguments about why it is better to see activities, props and prototypes as mainly constitutive rather than as only representative. Video prototypes on DVD and seven publications are included in the thesis.

Soft processing engines make FPGA programming simpler for software programmers. TILT is a multithreaded soft processing engine that contains multiple deeply pipelined and varying latency functional units. In this thesis, we present a compiler framework for compiling and scheduling for TILT. By using the compiler to generate schedules and manage hardware we create computationally dense designs (high throughput per hardware area) which make compelling processing engines. High schedule density is achieved by mixing instructions from different threads and by prioritizing the longest path of data flow graphs. Averaged across benchmark kernels we can achieve 90% of the theoretical throughput, and can reduce the performance gap relative to custom hardware from 543x for a scalar processor to only 4.41x by replicating TILT cores up to a comparable area cost. We also present methods of quickly navigating the design space and predicting the area of hardware configurations.