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This thesis presents an interactive computerised teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software for digital logic design. Several existing digital logic educational software are available, however these existing programs were found to be unsuitable for our use in providing alternative mode subject delivery. This prompted the development of a Microsoft Windows TM tutorial suite, called WinLogiLab. WinLogiLab comprises of a set of tutorials that uses student provided input data, to perform the initial design steps for digital Combinatorial and Sequential logic circuits. The combinatorial tutorials are designed to show the link between Boolean Algebra and Digital Logic circuits, and follows the initial design steps: from Boolean algebra, truth tables, to Exact and the Heuristic minimisation techniques, to finally produce the combinatorial circuit. Similarly, the sequential tutorials can design simple State Machine Counters, and can model more complex Finite State Automata.

This paper details the design and simulation of a fault-tolerant Quantum-dot Cellular Automata (QCA) NOT gate. A version of the standard NOT gate can be constructed to take advantage to the ability to easily integrate redundant structures into a QCA design. The fault-tolerant characteristics of this inverter are analyzed with QCADesigner v2.0.3 (Windows version) simulation software. These characteristics are then compared with the characteristics of two other non-redundant styles of NOT gates. The redundant version of the gate is more robust than the standard style for the inverter. However, another simple inverter style seems to be even more than this fault-tolerant design. Both versions of the gate will need to be studied further in the future to determine which design is most practical. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering / "July 2006." / Includes bibliographic references (leaves 31-33)

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This research pursues the use of powerful BDD-based functional circuit analysis to evaluate some approaches to test set generation. Functional representations of the circuit allow the measurement of information about faults that is not directly available through circuit simulation methods, such as probability of random detection and test-space overlap between faults. I have created a software tool that performs experiments to make such measurements and augments existing test generation strategies with this new information. Using this tool, I explored the relationship of fault model difficulty to test set length through fortuitous detection, and I experimented with the application of function-based methods to help reconcile the traditionally opposed goals of making test sets that are both smaller and more effective.

<p>Nanoscale devices offer the technological advances to enable a new era in computing. Device sizes at the molecular-scale have the potential to expand the domain of conventional computer systems to reach into environments and application domains that are otherwise impractical, such as single-cell sensing or micro-environmental monitoring.</p><p>New potential application domains, like biological scale computing, require processing elements that can function inside nanoscale volumes (e.g. single biological cells) and are thus subject to extreme size and resource constraints. In this thesis we address these critical new domain challenges through a synergistic approach that matches manufacturing techniques, circuit technology, and architectural design with application requirements. We explore and vertically integrate these three fronts: a) assembly methods that can cost-effectively provide nanometer feature sizes, b) device technologies for molecular-scale computing and sensing, and c) architectural design techniques for nanoscale processors, with the goal of mapping a potential path toward achieving molecular-scale computing.</p><p>We make four primary contributions in this thesis. First, we develop and experimentally demonstrate a scalable, cost-effective DNA self-assembly-based fabrication technique for molecular circuits. Second, we propose and evaluate Resonance Energy Transfer (RET) logic, a novel nanoscale technology for computing based on single-molecule optical devices. Third, we design and experimentally demonstrate selective sensing of several biomolecules using RET-logic elements. Fourth, we explore the architectural implications of integrating computation and molecular sensors to form nanoscale sensor processors (nSP), nanoscale-sized systems that can sense, process, store and communicate molecular information. Through the use of self-assembly manufacturing, RET molecular logic, and novel architectural techniques, the smallest nSP design is about the size of the largest known virus.</p> / Dissertation

This research pursues the use of powerful BDD-based functional circuit analysis to evaluate some approaches to test set generation. Functional representations of the circuit allow the measurement of information about faults that is not directly available through circuit simulation methods, such as probability of random detection and test-space overlap between faults. I have created a software tool that performs experiments to make such measurements and augments existing test generation strategies with this new information. Using this tool, I explored the relationship of fault model difficulty to test set length through fortuitous detection, and I experimented with the application of function-based methods to help reconcile the traditionally opposed goals of making test sets that are both smaller and more effective.

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