Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

This dissertation studies the design of an efficient adaptive digital baseband predistorter for modern cellular handsets that combines low power consumption, low implementation complexity, and high performance. The proposed enhancements are optimized for hardware implementation. We first present a thorough study of the optimal spacing of linearly-interpolated lookup table predistorters supported by theoretical calculations and extensive simulations. A constant-SNR compander that increases the predistorter's supported input dynamic range is derived. A corresponding low-complexity approximation that lends itself to efficient hardware design is also implemented in VHDL and synthesized with the Synopsys Design Compiler. This dissertation also proposes an LMS-based predistorter adaptation that is optimized for hardware implementation and compares the effectiveness of the direct and indirect learning architectures. A novel predistorter design with quadrature imbalance correction capability is developed and a corresponding adaptation scheme is proposed. This robust predistorter configuration is designed by combining linearization and I/Q imbalance correction into a single function with the same computational complexity as the widespread complex-gain predistorter.

Les travaux présentés lors de cette thèse s’inscrivent dans le cadre des réseaux de microsystèmes communicants dont les réseaux de capteurs sont l’exemple le plus connu. La problématique adressée est la conception d’une interface radio communicante répondant aux besoins spécifiques des microsystèmes communicants : simplicité, faible coût, faible consommation, faible encombrement, haut débit et reconfigurabilité. Les technologies actuelles sans fil comme le WiFi, le Bluetooth, et Zigbee ne sont pas en mesure de répondre à ces contraintes spécifiques. L’étude se focalise sur la technologie IR-UWB (Impulse Radio Ultra-WideBand). Dans un premier temps, une étude conjointe sur la capacité du canal et l’implémentation matérielle est menée pour déterminer l’architecture optimale des émetteurs-récepteurs en IR-UWB. Cette étude propose l’utilisation d’une architecture multi bandes IR-UWB (MB-IR-UWB) à implémentation mixte à 60 GHz avec des antennes directives. Cette solution est optimisée sur les critères de débit et puissance consommée. Afin de supporter l’ensemble des besoins des applications des réseaux de microsystèmes communicants et l’évolution de l’environnement d’opération, la reconfigurabilité doit être implémentée dans les émetteur-récepteurs proposés. Ces travaux présentent une proposition de reconfigurabilité par paramètres, qui permet de supporter la plus grande gamme de reconfigurabilités multi propriétés (débit, taux d’erreur, portée, puissance consommée, …) de l’état de l’art. Enfin, pour valider par la mesure les travaux sur la reconfigurabilité et sur les architectures d’émetteur-récepteurs IR-UWB, des implémentations FPGA et ASIC sont réalisées. Un nouveau procédé de synchronisation et démodulation conjointe reconfigurable est proposé dans le récepteur IR-UWB BPSK S-Rake. Les mesures montrent que le circuit de traitement proposé améliore les performances en synchronisation, démodulation, efficacité, débit du réseau, consommation et complexité du circuit. L’émetteur-récepteur IR-UWB reconfigurable proposé atteint un débit et une gamme de reconfigurabilité supérieure à l’état de l’art. / The research work presented in this thesis is situated in the framework of wireless sensor networks (WSNs). The issue addressed is the design of a radio interface answering the specific needs of WSNs: simplicity, low cost, low power, small size, high data rate and reconfigurability. Current wireless technologies like WiFi, Bluetooth, and Zigbee are not able to respond to these requirements. Thus this study focuses on Impulse Radio Ultra-WideBand (IR-UWB) technology. At first, a joint study of the channel capacity and the hardware implementation is carried out to determine the optimal architecture of IR-UWB transceivers. This study proposes an architecture using multi-band IR-UWB (MB-UWB-IR) with a mixed implementation at 60 GHz with directional antennas. This solution is optimized according to the criteria of data rate and power consumption. To support the all the needs of WSN applications and to adapt to the evolution of the WSN’s environment, reconfigurability must be implemented in the proposed IR-UWB transceiver. This thesis presents a new solution: the reconfigurability by parameters. It supports the widest range of multi-property reconfigurability (with respect to data rate, bit error rate, radio range, power consumption, ...) of the state of the art. Finally, to validate these techniques by measurements, FPGA and ASIC implementations are realized by using the reconfigurability and the IR-UWB transceiver architecture proposed. A new method for joint synchronization and demodulation is proposed for a reconfigurable IR-UWB BPSK S-Rake receiver. The measurements show that the proposed technique improves the circuit performance: synchronization, demodulation, efficiency, network throughput, power consumption and complexity of the circuit. The proposed IR-UWB reconfigurable transceiver achieves a data rate and a wider range of reconfigurability compared to the state of the art