Dans la chaine de développement des circuits, une attention particulière doit être portée sur le comportement en fiabilité des dispositifs MOS comme briques de base des circuits avancés CMOS lors du développement d’une technologie. Au niveau du dispositif, les comportements des différents mécanismes de dégradation sont caractérisés. A l’opposé dans le prototype final, le produit est caractérisé dans des conditions accélérées de vieillissement, mais seuls des paramètres macroscopiques peuvent être extraits. Un des objectifs de cette thèse a été de faire le lien entre le comportement en fiabilité d’un circuit ou système et ses briques élémentaires. Le second point important a consisté à développer des solutions de tests dites ‘intelligentes’ afin d’améliorer la testabilité et le gain de place des structures, pour mettre en évidence le suivi du vieillissement des circuits et la compensation des dégradations. Une autre famille de solutions a consisté à reproduire directement dans la structure l’excitation ou la configuration réelle vue par les dispositifs ou circuits élémentaires lors de leur vie d’utilisation (lab in situ). / In the circuit development, specific attention must be paid to the MOS device reliability as a building block as well as a prototype reference circuit (CMOS) during the technology development. At device level, the different degradation mechanisms are characterized. In the final prototype, the product is characterized in accelerated aging conditions, but only the macroscopic parameters can be extracted. One objective of this thesis has been to link the circuit or system reliability and its building blocks. Also, the second important point has consisted in the development of 'smart' test solutions to improve testability and gain up structures so as to highlight the circuits aging monitoring and degradation compensation. Another family of ‘smart’ solutions has involved reproducing directly in the structure the excitement or the actual configuration as it is seen by elementary circuits or devices during their usage life (lab in situ).

A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly. A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge. The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports. Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays. Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values. The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.

Tato diplomová práce se zabývá návrhem sekvenčních digitálních obvodů s ohledem na optimalizaci zpoždění. V práci je popsána problematika dvou technik, které jsou běžně používané při optimalizaci – stručně je popsána technika tzv. synchronizace registrů (angl. retiming), větší pozornost je však věnována technice tzv. zřetězení (angl. pipelining). V rámci praktické části byla vypracována forma abstrakce sekvenčních digitálních obvodů pomocí acyklických orientovaných grafů. Obvod je tak přenesen do roviny, ve které je jednodušší jej transformovat. Zároveň je představen nástroj pro polo-automatickou optimalizaci digitálních obvodů vyvíjených v prostředí Xilinx ISE Design Suite využitím techniky zřetězení.

This project deals with combinational digital circuits and their optimization. First there are presented main levels of abstraction utilized in the design of combinational digital circuits. Afterwards different methods are surveyed for optimization of combinational digital circuits. The next part of this project is mainly devoted to evolutionary algorithms, their common characteristics and branches: genetic algorithms, evolutionary strategies, evolutionary programming and genetic programming. The variant of genetic programming called Cartesian Genetic Programming (CGP) and the use of CGP in various areas, particularly in the synthesis and optimization of combinational logic circuits are described in detail. The project also discusses some modifications of CGP and the scalability problem of evolutionary circuit design. Consequential part of this thesis describes the method for evolution resynthesis of combinational digital circuits. There is description of design, especially the method of splitting circuits into subcircuits, and implementation details. Finally experiments with these method and their results are described.

This project deals with evolutionary design of electronic circuits with an emphasis on digital circuits. It describes the theoretical basics for the evolutionary design of circuits on computer systems, including the explanation of Genetic Programming and Evolutionary Strategies, possible design levels of electronic circuits, CMOS technology overview, also the overview of the most important evolutionary circuits design methods like development and Cartesian Genetic Programming. Next introduced is a new method of digital circuits design on the transistor level, which is based on CGP. Also a design system using this new method is introduced. Finally, the experiments performed with this system are described and evaluated.

Optical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance lost due to process variations. Then we study the impact of positioning of tunable buffers in the clock tree. In course of our study it was observed that the greatest benefit from tunable buffer placement can be derived, when the clock tree is synthesized with future tuning considerations. Accordingly, we present a clock tree synthesis procedure which offers very good mitigation against process variation, as borne out by the results. The results show that without any design intervention, an average improvement of 9% is achieved by our tuning system. However, when the clock tree is synthesized based on static timing information with tuning buffer placement considerations, much larger performance improvement is possible. In one example, performance improved by as much as 18%.

Soft multiprocessor systems exploit the plentiful computational resources available in field programmable devices. By virtue of their adaptability and ability to support coarse grained parallelism, they serve as excellent platforms for rapid prototyping and design space exploration of embedded multiprocessor applications. As complex applications emerge, careful mapping, processor and interconnect customization are critical to the overall performance of the multiprocessor system. In this thesis, we have developed an automated scalable framework to efficiently map applications written in a high-level programmer-friendly language to customizable soft-cores. The framework allows the user to specify the application in a high-level language called Streamit. After an initial analysis of the application, a soft multiprocessor system is generated automatically using a set of customizable SPREE processors which communicate with each other over point-to-point FIFO connections. Several micro-architectural features of the processors are then automatically customized on a per-application basis to improve system area, performance and power consumption. The efficiency and scalability of this approach has been validated using a diverse set of eight audio, video and signal processing benchmarks on soft multiprocessor systems consisting of one to sixteen processors. Results show that generated soft multiprocessor systems consisting of sixteen processors can offer up to 6x speedup over a conventional single processor system. Our experiments with soft multiprocessor interconnection networks show that point-to-point topologies perform approximately 2x better than mesh topologies. Finally, we demonstrate that application-specific customizations on the instruction set, memory size, and inter-processor buffer size can improve the area and performance of the generated soft multiprocessor systems. The developed framework facilitates rapid design space exploration of soft multiprocessors.

Power dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S.

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.

The focus of this thesis is to explore the automation technology used in the modern entertainment industry. Upon completion of my thesis, I will deliver a working prototype of the chosen technology and present its capabilities in a choreographed show.