This thesis focuses on the study, implementation and improvement of a digital Generator Control Unit (GCU) for a high-speed synchronous brushless generator. The control of variable frequency power system, a preferred candidate in More Electric Aircraft (MEA), becomes a big challenge. Compared with conventional analog GCU, digital GCU is a future trend due to the properties such as easy tuning, modification and no aging. Control approaches adopted in the new GCU design is introduced. It has multiloop structure and model-based characteristics. Sensorless rotor position detection was used to finish Park transformation. DSP+FPGA based controller hardware was developed in the lab. A set of hardware was designed to implement the control algorithms. VHDL-based software was developed for FPGA, which is working as a bridge between DSP and peripheral circuits. C-based software was designed to implement control algorithm inside DSP. A testbed system was developed according to the lab capacity of CPES. The complete load transit responses were tested according to the standard ISO1540 and EN8420. Good match between simulation and experiment has been reached. Compared with benchmark controller, great improvement in both steady state and dynamic performance is realized. A feasibility of using digital GCU in the next generation aircraft has been proved preliminarily. However, the challenge of reliability issues in digital system and software still needs further attention. / Master of Science

Recently, constant-on-time V2 control is more and more popular in industry products due to features of high light load efficiency, simple implementation and fast transient response. In many applications such as cell phone, camera, and other portable devices, low-ESR capacitors such as ceramic caps are preferred due to small size and small output voltage ripple requirement. However, for the converters with ceramic caps, the conventional V2 control suffers from the sub-harmonic oscillation due to the lagging phase of the capacitor voltage ripple relative to the inductor current ripple. Two solutions to eliminate sub-harmonic oscillations are discussed in [39] and the small-signal models are also derived based on time-domain describing function. However, the characteristic of constant-on-time V2 with external ramp is not fully understood and no explicit design guideline for the external ramp is provided. For digital constant on-time V2 control, the high resolution PWM can be eliminated due to constant on-time modulation scheme and direct output voltage feedback [43]. However, the external ramp design is not only related to the amplitude of the limit-cycle oscillation, but also very important to the stability of the system. The previous analysis is not thorough since numerical solution is used. The primary objective of this work is to gain better understanding of the small-signal characteristic for analog and digital constant-on-time V2 with ramp compensations, and provide the design guideline based on the factorized small-signal model. First, constant on-time current-mode control and constant on-time V2 control are reviewed. Generally speaking, constant-on-time current mode control does not have stability issues. However, for constant-on-time V2 control with ceramic caps, sub-harmonic oscillation occurs due to the lagging phase of the capacitor voltage ripple. External ramp compensation and current ramp compensation are two solutions to solve the problem. Previous equivalent circuit model extended by Ray Ridley's sample-and-hold concept is not applicable since it fails to consider the influence of the capacitor voltage ripple. The model proposed in [39] successfully considers the influence from the capacitor voltage ripple by using time-domain describing function method. However, the characteristic of constant-on-time V2 with external ramp is not fully understood. Therefore, more research focusing on the analysis is needed to gain better understanding of the characteristic and provide the design guideline for the ramp compensations. After that, the small-signal model and design of analog constant on-time V2 control is investigated and discussed. The small-signal models are factorized and pole-zero movements are identified. It is found that with increasing the external ramp, two pairs of double poles first move toward each other at half of switching frequency, after meeting at the key point, the two double poles separate, one pair moves to a lower frequency and the other moves to a higher frequency while keeping the quality factor equal to each other. For output impedance, with increasing the external ramp, the low frequency magnitude also increases. The recommended external ramp is around two times the magnitude at the key point K. When Duty cycle is larger, the damping performance is not good with only external ramp compensation, unless very high switching frequency is used. With current ramp compensation, it is recommended to design the current ramp so that the quality factor of the double pole is around 1. With current ramp compensation, the damping can be well controlled regardless of the circuit parameters. Next, the small-signal analysis and design strategy is also extended to digital constant on-time V2 control structure which is proposed in [43]. It is found that the scenario is very similar as analog constant on-time V2 control. The external ramp should be designed around the key point to improve the dynamic performance. The sampling effects of the output voltage require a larger external ramp to stabilize digital constant-on-time V2 control while suffers only a little bit of damping performance. One simple method for measuring control-to-output transfer functions in digital constant-on-time V2 control is presented. The experimental results verify the small-signal analysis except for the high frequency phase difference which reveals the delay effects in the circuit. Load transient experimental results prove the proposed design guideline for digital constant on-time V2 control. As a conclusion, the characteristics of analog and digital constant-on-time V2 control structures are examined and design guidelines are proposed for ramp compensations based on the factorized small-signal model. The analysis and design guideline are verified with simplis simulation and experimental results. / Master of Science

It can be expected that digital controllers will be increasingly used in low voltage, high-current and high frequency voltage regulator modules (VRMs) where conventional analog controllers are currently preferred because of the cost and performace reasons. However, there are still remaining two significant challenges for the spread of the digital control techniques: quantization effects and the delay effects. Quantization effects might introduce the limit cycle oscillations (LCOs) to the converter, which will generate the stability issues. Actually, LCOs can not be totally eliminated theoretically. One way to reduce the possibilities of LCOs is to employ a high resolution Digital Pulse-Width-Modulator (DPWM). However, designing such a DPWM which can meet the requirements of VRMs application requires ultra-high system clock frequency, up to several GHz. Such high frequency is impractical due to huge power consumption. Hybrid DPWM might be an alternative solution but will occupy large silicon area. Single phase digital constant on-time modulation method is another good candidate to improve the DPWM resolution without adding too much cost. However, directly extending this method to multi-phase application, which is the prevalent structure in VRMs application, will introduce some issues. With more phases in parallel, the duty cycle resolution will drop more. To solove the mentioned issue, this work proposed a multi-phase digital constant on-time modulation method. The proposed method will control the control voltage to alternate between two adjacent values, or dither, within one switching period. The outcome is that the phase duty cycle's resolution is improved and independent on phase number. Compared with conventional constant frequency modulation method, the proposed method can achieve about 10 times higher duty cycle resolution for the VRM application. The effectiveness of the proposed method is verified by the simulation as well as the experiment results. Delay effect is another concern for the digital controlled VRMs. There exist several types of delays in the digital feedback loop, including the ADC conversion delay, digital compensator calculation delay, DPWM delay as well as some propagation delays. Usually these delays are inside the digital controller and it is hard to know the exact values. There are several papers talking about the small signal models of the digital voltage mode control. These models are valid only if all the delay terms are known exactly since each delay is considered separately. Actually, this process is not easy. Moreover, there is no literature talking about the complete small signal model of the digital VRMs. But in reallity, different implementations of the sampling process will give different impacts to the loop. This work proposed the small signal signal models of digital VRMs. The analysis is based on the assumptions that DPWM is a double-edge modulation and the sampling instants are aligned with the middle of one phase's off time. At first, the conversion and calculation delay is neglected. The focus of the modeling is on the small signal model of the current sampling methods and the DPWM delay. This model is valid for those digital controllers which have fast ADC and fast calculation capabilities. It is shown that even with a "fast" controller, the current sampling and DPWM might introduce some delay to the loop. After that, the conversion and calculation delay are considered into the modeling. Two time periods, T1ff and T1rr, are employed to describe the total delay effects in the control loop. It is observed that the total delay in the loop is integral times of sampling periods, which is never reported by any other literatures. Therefore, the proposed model only includes one delay term and the value of this delay can be found through a pre-determined lookup table. Finally, the complete small signal model of the digital VRMs considering the conversion and calculation delay is proposed. This model is helpful for the researchers to find the delay effects in their control loop based on the range of the total physical delay in the controller. With the derived small signal mondels of digital VRMs, the design guildeline for AVP control are presented. The digital active-droop control is employed and it borrows the concept of constant output impedance control from the analog world. Two design examples are provided for the verification. / Master of Science

This thesis focuses on the study, implementation and improvement of a digital controller for a power factor correction (PFC) converter. The development of the telecommunications industry and the Internet demands reliable, cost-effective and intelligent power. Nowadays, the telecommunication power systems have output current of up to several kilo amperes, consisting of tens of modules. The high-end server system, which holds over 100 CPUs, consumes tens of kilowatts of power. For mission-critical applications, communication between modules and system controllers is critical for reliability. Information about temperature, current, and the total harmonic distortion (THD) of each module will enable the availability of functions such as dynamic temperature control, fault diagnosis and removal, and adaptive control, and will enhance functions such as current sharing and fault protection. The dominance of analog control at the modular level limits system-module communications. Digital control is well recognized for its communication ability. Digital control will provide the solution to system-module communication for the DC power supply. The PFC converter is an important stage for the distributed power system (DPS). Its controller is among the most complex with its three-loop structure and multiplier/divider. This thesis studies the design method, implementation and cost effectiveness of digital control for both a PFC converter and for an advanced PFC converter. Also discussed is the influence of digital delay on PFC performance. A cost-effective solution that achieves good performance is provided. The effectiveness of the solution is verified by simulation. The three level PFC with range switch is well recognized for its high efficiency. The range switch changes the circuit topology according to the input voltage level. Research literature has discussed the optimal control for both range-switch-off and range-switch-on topologies. Realizing optimal analog control requires a complex structure. Until now optimal control for the three-level PFC with analog control has not been achieved. Another disadvantage of the three-level PFC is the output capacitor voltage imbalance. This thesis proposes an active balancing solution to solve this problem. / Master of Science

The realisation of signal processing algorithms in fixed-point offers substantial performance advantages over floating-point realisations. However, it is widely acknowledged that the task of realising algorithms in fixed-point is a challenging one with limited tool support. This thesis examines various aspects related to the translation of algorithms, given in infinite precision or floating-point, into fixed-point. In particular, this thesis reports on the implementation of a given algorithm, an EDFA (Erbium-Doped Fibre Amplifier) control algorithm, on a FPGA (Field Programmable Gate Array) using fixed-point arithmetic. An analytical approach is proposed that allows the automated realisation of algorithms in fixedpoint. The technique provides fixed-point parameters for a given floating-point model that satisfies a precision constraint imposed on the primary output of the algorithm to be realised. The development of a simulation framework based on this analysis allows fixed-point designs to be generated in a shorter time frame. Albeit being limited to digital algorithms that can be represented as a data flow graph (DFG), the approach developed in the thesis allows for a speed up in the design and development cycle, reduces the possibility of error and eases the overall effort involved in the process. It is shown in this thesis that a fixed-point realisation of an EDFA control algorithm using this technique produces results that satisfy the given constraints.

The optimal estimation theory of the Wiener-Kalman filter is extended to cover the situation in which the number of memory elements in the estimator is restricted. A method, based on the simultaneous diagonalisation of two symmetric positive definite matrices, is given which allows the weighted least square estimation error to be minimised. A control system design method is developed utilising this estimator, and this allows the dynamic controller in the feedback path to have a low order. A 12-order once-through boiler model is constructed and the performance of controllers of various orders generated by the design method is investigated. Little cost penalty is found even for the one-order controller when compared with the optimal Kalman filter system. Whereas in the Kalman filter all information from past observations is stored, the given method results in an estimate of the state variables which is a weighted sum of the selected information held in the storage elements. For the once-through boiler these weighting coefficients are found to be smooth functions of position, their form illustrating the implicit model reduction properties of the design method. Minimal-order estimators of the Luenberger type also generate low order controllers and the relation between the two design methods is examined. It is concluded that the design method developed in this thesis gives better plant estimates than the Luenberger system and, more fundamentally, allows a lower order control system to be constructed. Finally some possible extensions of the theory are indicated. An immediate application is to multivariable control systems, while the existence of a plant state estimate even in control systems of very low order allows a certain adaptive structure to be considered for systems with time-varying parameters.

Les travaux de cette thèse portent sur l’analyse de stabilité et la synthèse de commandes robustes pour les systèmes linéaires à commutation en temps discret avec des incertitudes polytopiques et des incertitudes sur la loi de commutation. On considère des lois de commutations arbitraires et on montre que l’utilisation des fonctions de Lyapunov commutées dépendant de paramètres permet de déterminer des critères de stabilité et de stabilisation robuste moins conservatifs. Ensuite, des conditions de stabilité robuste pour les systèmes en temps discret avec une loi de commutation incertaine sont présentées en termes de temps minimum de séjour. Les résultats obtenus s’avèrent utiles dans le contexte de la commande numérique des systèmes continus en présence d’imprécisions sur les instants d’échantillonnage et d’application des commandes. Nous montrons comment une modélisation à base d’évènements permet de ramener le problème original à un problème spécifique aux systèmes à commutation avec des incertitudes polytopiques. Les résultats sont étendus au cas des systèmes à commutation continus commandés par des correcteurs numériques / This PhD thesis is dedicated to the study of robust stability analysis and control synthesis for discrete time uncertain switching systems under arbitrary switching. Polytopic uncertainties are considered. We show that Lyapunov functions that depend on the uncertain parameter and that take into account the structure of the system may be used in order to reduce the conservatism related to uncertainty problems. Next, we consider the case of discrete time switched systems that are stabilized by a switched state feedback for which the switching signal may be temporary uncertain. Dwell time conditions for stability analysis of such systems are given. These results are usefull in the context of continuous time are stabilized via a computer when uncertainties occur on the sampling and actuation events. We present a new event based discrete-time model and we show that the stabilizability of this system can be achieved by finding a control for a switched polytopic system. The methodology is extended to the case of switched system

Digital control needs discrete time models, but conversion from continuous time, fed by a zero order hold, to discrete time introduces sampling zeros which are outside the unit circle, i.e. non-minimum phase (NMP) zeros, in the majority of the systems. Also, some systems are already NMP in continuous time. In both cases, the inverse problem to find the input required to maintain a desired output tracking, produces an unstable causal control action. The control action will grow exponentially every time step, and the error between time steps also grows exponentially. This prevents many control approaches from making use of inverse models. The problem statement for the existing stable inverse theorem is presented in this work, and it aims at finding a bounded nominal state-input trajectory by solving a two-point boundary value problem obtained by decomposing the internal dynamics of the system. This results in the causal part specified from the minus infinity time; and its non-causal part from the positive infinity time. By solving for the nominal bounded internal dynamics, the exact output tracking is achieved in the original finite time interval. The new stable inverses concepts presented and developed here address this instability problem in a different way based on the modified versions of problem states, and in a way that is more practical for implementation. The statements of how the different inverse problems are posed is presented, as well as the calculation and implementation. In order to produce zero tracking error at the addressed time steps, two modified statements are given as the initial delete and the skip step. The development presented here involves: (1) The detection of the signature of instability in both the nonhomogeneous difference equation and matrix form for finite time problems. (2) Create a new factorization of the system separating maximum part from minimum part in matrix form as analogous to transfer function format, and more generally, modeling the behavior of finite time zeros and poles. (3) Produce bounded stable inverse solutions evolving from the minimum Euclidean norm satisfying different optimization objective functions, to the solution having no projection on transient solutions terms excited by initial conditions. Iterative Learning Control (ILC) iterates with a real world control system repeatedly performing the same task. It adjusts the control action based on error history from the previous iteration, aiming to converge to zero tracking error. ILC has been widely used in various applications due to its high precision in trajectory tracking, e.g. semiconductor manufacturing sensors that repeatedly perform scanning maneuvers. Designing effective feedback controllers for non-minimum phase (NMP) systems can be challenging. Applying Iterative Learning Control (ILC) to NMP systems is particularly problematic. Incorporating the initial delete stable inverse thinkg into ILC, the control action obtained in the limit as the iterations tend to infinity, is a function of the tracking error produced by the command in the initial run. It is shown here that this dependence is very small, so that one can reasonably use any initial run. By picking an initial input that goes to zero approaching the final time step, the influence becomes particularly small. And by simply commanding zero in the first run, the resulting converged control minimizes the Euclidean norm of the underdetermined control history. Three main classes of ILC laws are examined, and it is shown that all ILC laws converge to the identical control history, as the converged result is not a function of the ILC law. All of these conclusions apply to ILC that aims to track a given finite time trajectory, and also apply to ILC that in addition aims to cancel the effect of a disturbance that repeats each run. Having these stable inverses opens up opportunities for many control design approaches. (1) ILC was the original motivation of the new stable inverses. Besides the scenario using the initial delete above, consider ILC to perform local learning in a trajectory, by using a quadratic cost control in general, but phasing into the skip step stable inverse for some portion of the trajectory that needs high precision tracking. (2) One step ahead control uses a model to compute the control action at the current time step to produce the output desired at the next time step. Before it can be useful, it must be phased in to honor actuator saturation limits, and being a true inverse it requires that the system have a stable inverse. One could generalize this to p-step ahead control, updating the control action every p steps instead of every one step. It determines how small p can be to give a stable implementation using skip step, and it can be quite small. So it only requires knowledge of future desired control for a few steps. (3) Note that the statement in (2) can be reformulated as Linear Model Predictive Control that updates every p steps instead of every step. This offers the ability to converge to zero tracking error at every time step of the skip step inverse, instead of the usual aim to converge to a quadratic cost solution. (4) Indirect discrete time adaptive control combines one step ahead control with the projection algorithm to perform real time identification updates. It has limited applications, because it requires a stable inverse.

Abstract not available

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.