The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

The main goal of this thesis is to develop an active thermal management control scheme for multi-phase current mode buck converters in order to improve the long term reliability of the converters. A thermal management unit (TMU) with independent linear compensators for the thermal loops is incorporated into the existing digital controller to regulate the current through each phase so that equal temperature distribution is achieved across all phases. A lumped parameter thermal model of the multi-phase converter is built as the basis of the TMU. MATLAB simulation results are used to verify the TMU concept. Experimental results from a digitally controlled 12 V to 1 V, 50 A, 250 kHz four-phase peak current mode buck converter demonstrate the effectiveness of the proposed thermal management technique in the presence of uneven air flow. The steady-state performance, dynamic transient load performance, effect of gate drive voltage and efficiency measurements are investigated and discussed.

Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.

Switched mode power supplies (SMPS) are being extensively used in most power conversion processes. The analysis, design and modeling processes of hard-switched converters are mature, where the switching frequency was limited to a few 10's of kHz. The present direction of evolution m SMPS is towards higher efficiency and higher power density. These twin objectives demand high switching frequency and low overall losses. Soft switching results in practically zero switching losses and extends the switching frequency to 100's of kHz and beyond. This thesis presents novel variants of push-pull and half-bridge DC-DC converters with soft switching properties. The proposed topology uses two additional switches and two diodes. The additional switches introduce freewheeling intervals m the circuit and enable loss-less switching. Switch stress, control and small signal model are similar to hard-switched PWM converter. Synchronous rectifiers are used in the ZVS push-pull converter to achieve high efficiency. It is interesting to see that the drives for the synchronous rectifier device are practically the same as the additional switches. The contributions made in this thesis are 1) Idealized analysis and design methodology for the proposed converters. 2) Validation of the design through circuit simulation as well as prototypes - a 300kHz, 200W push-pull converter and a 300kHz, 640W half-bridge converter. 3) Closed loop control design for desired bandwidth and accuracy Verification of loop gain through network analyzer instrumental for the same The loop gain bandwidth achieved is about 30kHz for the push-pull converter and 20kHz for half-bridge converter. An appendix has been devoted to explain the use of network analyzer. Characterization of coil, transformer and capacitor are explained in detail. Measurement techniques for measuring the small signal parameters of power supply are also explained in the appendix.

Switched mode power supplies (SMPS) have found wide spread acceptance in all power processing applications. The design demand is moving towards higher power densities. For reduction in size and weight, it is imperative to process the power at a higher switching frequency. High switching frequency requires soft switching techniques to reduce the switching losses. Several families of soft switching converters have emerged in the past two decades. Analysis and modelling methods have been proposed in relation with these topologies. Active clamp converters are the recently introduced soft switching topologies. Steady state analysis and model of these converters have been reported in literature. This thesis presents a unified equivalent circuit oriented model for the family of active clamp converters. Analytical expressions for DC conversion ratio in terms of pole current and throw voltage are derived for all the DC-DC converters with active clamp. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. The proposed equivalent circuit models are valid for both steady-state and dynamic performance. A spread sheet based design is presented for the basic DC-DC converters with active clamp. A prototype design following the spreadsheet is made. The performance of the same is validated and verified by simulation and measurements. Steady state and dynamic results are presented. The stability criterion for the active clamp converters under current programming is investigated. The same is verified through simulation and validated on a current programmed active clamp converter prototype. The active clamp converters suffer from a few disadvantages: Higher VA ratings of switches, load dependent ZVS performance and increased component count. Several soft switching topologies have been reported in literature. Efficiency improvement and increase in switching frequency are obtained to different degrees. This thesis proposes a new family of soft switching converters. This family of converters switch at constant frequency and maintains the advantages of traditional PWM converters. The proposed topology employs an auxiliary circuit to achieve soft switching. The auxiliary circuit consists of a dependent voltage source, an auxiliary switch, a series diode and a set of resonant elements (Inductor and capacitor). The switching transitions of both the active switch and the auxiliary switch are lossless. The novelty in the proposed circuit is the method of generating the dependent source required to enable zero current switching of the auxiliary switch. The dependent source is realized by a coupled winding in the energy storage inductor or tapped from the energy transfer transformer of non-isolated and isolated converters respectively. The proposed topology is applicable to most of the isolated and non-isolated DC-DC converters. The circuit equations governing the sub-intervals of the converter are expressed in terms of pole current and throw voltage. With such a definition, performance results and the design equations are identical for all types of DC-DC converters. Equivalent circuit models are obtained for the whole family of DC-DC converters. The proposed model is valid for steady state and dynamic performance. Analytical expressions of DC conversion ratio for all topologies, in terms of pole current and throw voltage are derived. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. Design guidelines are established for the whole family of proposed converters; the same are validated through prototype converters.

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

L’utilisation des alimentations à découpage (SMPSs : switched mode power supplies) est à présent largement répandue dans des systèmes embarqués en raison de leur rendement. Les exigences technologiques de ces systèmes nécessitent simultanément une très bonne régulation de tension et une forte compacité des composants. SEPIC (Single-Ended Primary Inductor Converter) est un convertisseur à découpage DC/DC qui possède plusieurs avantages par rapport à d’autres convertisseurs de structure classique. Du fait de son ordre élevé et de sa forte non linéarité, il reste encore peu exploité. L’objectif de ce travail est d’une part le développement des stratégies de commande performantes pour un convertisseur SEPIC et d’autre part l’implémentation efficace des algorithmes de commande développés pour des applications embarquées (FPGA, ASIC) où les contraintes de surface silicium et le facteur de réduction des pertes sont importantes. Pour ce faire, deux commandes non linéaires et deux observateurs augmentés (observateurs d’état et de charge) sont exploités : une commande et un observateur fondés sur le principe de mode de glissement, une commande prédictive et un observateur de Kalman étendu. L’implémentation des deux lois de commande et l’observateur de Kalman étendu sont implémentés sur FPGA. Une modulation de largeur d’impulsion (MLI) numérique à 11-bit de résolution a été développée en associant une technique de modulation Δ-Σ de 4-bit, un DCM (Digital Clock Management) segmenté et déphasé de 4-bit, et un compteur-comparateur de 3-bit. L’ensemble des approches proposées sont validées expérimentalement et constitue une bonne base pour l’intégration des convertisseurs à découpage dans les alimentations embarquées. / The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters