A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of the major obstacles in improving the accuracy and performance of mixed-signal IC applications. Using simple circuits, FSCL logic family can be interfaced with the existing CMOS family. Thus it can nearly eliminate the power noise issue in the mixed-signal IC design. In this thesis, design of a sinc3 decimation filter using the FSCL technique for a 2nd order delta-sigma modulator has been presented. Simulation results show that this particular decimation filter, using the newly developed FSCL technique, improves the performance of the mixed-signal system. / Graduation date: 1994

Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions. As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed. The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.

This thesis aims to design and develop camera electronics and image enhancement software for infrared detector arrays. It first discusses the camera electronics suitable for infrared detector arrays, then it concentrates on image enhancement software that are implemented including defective pixel correction, contrast enhancement, noise reduction and pseudo coloring. After that, testing and results of the implemented algorithms were presented. Camera electronics and circuit operation frequency are selected considering the available standard programmable devices and the output rate of the detector readout circuitry. The target device for implementation of algorithms was Xilinx Spartan &ndash / 3 XC3S1500 which is used in the camera tests at METU-MEMS Research and Applications Center. Considering the real time operation, the target clocking frequency for operation of the circuitry was selected as 2MHz. Image enhancement algorithms primarily aim to be implemented for 320 x 240 resolution detectors, however with parametric implementation, they aim to support other resolutions, including 160 x 120 and 640 x 512. In addition, all implementations aim to be modular and reusable. Various different approaches are used for image enhancement software: (i) defective pixel correction is achieved by using a selective median filtering approach, (ii) contrast enhancement is achieved by employing contrast stretching and histogram based methods, and (iii) noise reduction is achieved by implementing a spatial filter. In addition to these, four types of pseudo coloring methods were applied and tested. Test results show that defective pixel correction algorithm operates at 20.0 MHz, with 0.0 x 10-3 RMS error from its MATLAB prototype, and contrast enhancement algorithms are able to operate at 3.3 MHz, with an average of 545.0 x 10-3 RMS error. Spatial filtering for noise reduction operates at 20.0 MHz, with a 2.6 x 10-3 RMS. Pseudo-coloring operates at 125.0 MHz, with a 0.0 x 10-3 RMS deviation from its MATLAB prototype,

In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar. Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines Systems zur Inertialnavigation.

Low-power digital design has been a widely researched area for the past twenty years. The growing demand for mobile computing made low power an especially important quality for such systems and encouraged researchers to find new ways of reducing power dissipation. Aggressive voltage scaling was recently published as a new paradigm for reducing power dissipation in digital circuits and the use of soft-edge flip-flops is one such technique in this category. In this thesis, we propose a soft-edge flip-flop topology that is better suited to implement the soft-edge property compared to the previously published implementations. In addition, we present the effectiveness of the soft-edge flip-flop technique by applying it to a practical VLSI design implemented with the TSMC 0.18um standard cell library. Using HSIM transistor-level SPICE simulator, we show that at least 25% power reduction is achievable in the whole circuit with a negligible area overhead. / text

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

The ever increasing complexity and size of digital circuits complemented by Deep Sub Micron (DSM) technology trends today pose challenges to the efficient Design For Test (DFT) methodologies. Innovation is required not only in designing the digital circuits, but also in automatic test pattern generation (ATPG) to ensure that the pattern set screens all the targeted faults while still complying with the Automatic Test Equipment (ATE) memory constraints. DSM technology trends push the requirements of ATPG to not only include the conventional static defects but also to include test patterns for dynamic defects. The current industry practices consider test pattern generation for transition faults to screen dynamic defects. It has been observed that just screening for transition faults alone is not sufficient in light of the continuing DSM technology trends. Shrinking technology nodes have pushed DFT engineers to include Small Delay Defect (SDD) test patterns in the production flow. The current industry standard ATPG tools are evolving and SDD ATPG is not the most economical option in terms of both test generation CPU time and pattern volume. New techniques must be explored in order to ensure that a quality test pattern set can be generated which includes patterns for stuck-at, transition and SDD faults, all the while ensuring that the pattern volume remains economical. This thesis explores the use of a “Top-Off” ATPG methodology to generate an optimal test pattern set which can effectively screen the required fault models while containing the pattern volume within a reasonable limit.

O argumento desta tese é delineado no bastidor da noção de 'programa‘. O termo 'programa‘ inclui, em seu significado, software (programa computacional) e programa de arquitetura. É tramado pelas diferentes instâncias da natureza projetual, em que interagem programa e projeto. Equaciona o fenômeno digital a partir das diferentes naturezas que o conceito de 'programa‘, como software e programa de arquitetura, pode assumir. Analisa a interação entre projetista, ‗programa‘, imagem e informação no projeto digital. Propõe a experimentação como forma de transcender as limitações impostas pelas regras programadas nos 'programas‘. / The thesis argument is delineated in the embroidery frame of the notion of 'program‘. The term 'program‘, includes in its meaning computational program and program of architecture. It is conspired by the different instances of design nature where 'program' and design interact. It equates the digital phenomenon from the different natures that can assume the concept of 'program' as software and as architecture program. It analyzes the interaction among designer, 'program', image and information in the digital design. It considers the experimentation as a way to exceed the limitations imposed by the programmed rules of the 'programs‘.

A crescente demanda por alto desempenho computacional e massivo processamento de dados tem impulsionado o desenvolvimento de sistemas-on-chip. Um dos alvos de implementação para sistemas digitais complexos são os dispositivos FPGA (Field-programmable Gate Array), muito utilizados para prototipação de sistemas e rápido desenvolvimento de produtos eletrônicos complexos. Certos aspectos ineficientes relacionados aos dispositivos FPGA estão relacionadas com degradação no desempenho e na potência consumida em relação ao projeto de hardware customizado. Neste contexto, esta dissertação de mestrado propõe um estudo sobre técnicas de otimização em FPGAs. Este trabalho apresenta uma revisão da literatura sobre os métodos de redução de potência e área aplicados ao projeto de FPGA. Técnicas para aumento de desempenho e aceleração do tempo de desenvolvimento de projetos são apresentadas com base em referencias clássicas e do estado-da-arte. O principal foco deste trabalho é discutir sobre as técnicas de alto nível e apresentar os resultados obtidos nesta área, comparando com os projetos HDL (Hardware Description Language) codificados a mão. Neste trabalho, é apresentado uma metodologia para o desenvolvimento rápido projetos digitais utilizando ambientes HLS (High-Level Synthesis. Estes métodos incluem eficiente particionamento de código de alto nível, para a correta exploração de diretivas de síntese em ferramentas HLS. Porém, o fluxo HLS não guiado apresentou pobres resultados de síntese quando comparado com modelos HDL codificado a mão. Para preencher essa lacuna, foi desenvolvido um método iterativo para exploração de espaço de projeto com o objetivo de melhorar os resultados de área. Nosso método é descrito em uma linguagem de script de alto nível e é compatível com o VivadoTM HLS Compiler. O método proposto é capaz de detectar pontos chave para otimização, inserção automatica de diretivas síntese e verificação dos resultados com objetivo de reduzir o consumo de área. Os resultados experimentais utlizando o método de DSE (Design Space Exploration) provaram ser mais eficazes que o fluxo HLS não guiado, em ao menos 50% para um processador VLIW e em 43% para um filtro FIR (Finite Impulse Response de 12a ordem. Os resultados em área, em termos de flip-flops, foram até 4X menores em comparação com o fluxo HLS não guiado, enquanto redução no desempenho ficou em cerca de 38%, no caso do processador VLIW. No exemplo do filtro FIR, a redução no número flip-flops chegou a 3X, sem relevante aumento no número de LUTs e redução no desempenho. / The increasing demand for high computational performance and massive data processing has driven the development of systems-on-chip. One implementation target for complex digital systems are FPGA (Field-programmable Gate Array) devices, heavily used for prototyping systems or complex and fast time-to-market electronic products development. Certain inefficient aspects of FPGA devices relate to performance and power degradation with respect to custom hardware design. In this context, this master thesis proposes a survey on FPGA optimization techniques. This work presents a literature review on methods of power and area reduction applied to FPGA designs. Techniques for performance increasing and design speedup enhancing will be presented based on classic and state-of-the-art academic works. The main focus of this work is to discuss high-level design techniques and to present the results obtained in synthesis examples we developed, comparing with hand-coded HDL (Hardware Description Language) designs. In this work we present our methodology for fast digital design development using High-Level Synthesis (HLS) environments. Our methods include efficient high-level code partitioning for proper synthesis directives exploration in HLS tools. However, a non-guided HLS flow showed poor synthesis results when compared to hand-coded HDL designs. To fill this gap, we developed an iterative design space exploration method aiming at improving the area results. Our method is described in a high-level script language and it is compatible with the Xilinx VivadoTM HLS compiler. Our method is capable of detecting optimization checkpoints, automatic synthesis directives insertion, and check the results aiming at reducing area consumption. Our Design Space Exploration (DSE) experimental results proved to be more efficient than non-guided HLS design flow by at least 50% for a VLIW (Very Long Instruction Word) processor and 62% for a 12th-order FIR (Finite Impulse Response) filter implementation. Our area results in terms of flip-flops were up to 4X lower compared to a non-guided HLS flow, while the performance overhead was around 38%, for the VLIW processor compilation. In the FIR filter example, the flip-flops reduction were up to 3X, with no relevant LUTs and performance overhead.

O presente trabalho de pesquisa disserta sobre como a aplicação de filosofia e princípios ágeis podem contribuir para a melhoria de resultados de produção de modelos tridimensionais para jogos digitais. Na área da informática, os métodos ágeis são amplamente utilizados para gerir projetos e equipes de desenvolvimento. Tais métodos são guiados pelo manifesto ágil, elaborado pelos principais profissionais do setor como forma de estabelecer um padrão. O manifesto ágil versa que indivíduos e interações são mais importantes que processos e ferramentas. Software em funcionamento é mais importante que documentação abrangente, bem como colaboração com o cliente é mais importante que negociação de contratos. Responder a mudanças é mais importante que seguir um plano. Pelo manifesto vê-se claramente uma tendência à valorização da pessoa frente ao processo, projeto ou produto, pois ela é o meio de realização destes. O manifesto ágil tem sua origem e fonte inspiradora na filosofia e princípios ágeis de Lean, utilizados pela Toyota em seu sistema de produção. Estima-se que para o desenvolvimento de boas práticas ágeis específicas para a produção de modelos tridimensionais para jogos seja uma oportunidade de melhor atuar na indústria, uma vez que com elas pode-se arranjar um padrão de desenvolvimento. Para se conseguir elencar tais práticas, busca-se isto na fundamentação teórica sobre jogos digitais, design e métodos ágeis. É apresentado um experimento prático, onde se faz um cruzamento dos dados coletados com um conjunto de melhores práticas ágeis adotadas para o desenvolvimento de modelos tridimensionais para ambiente de jogos digitais. Como resultados aponta-se que as práticas ágeis contribuem para o desenvolvimento de modelos desde que seu entendimento seja em todos os níveis organizacionais. Infere-se que o entendimento da filosofia Lean aplicada área de jogos digitais favorece o entendimento de quais práticas ágeis elencadas pode-se utilizar de fato. / This research presents how the application of agile principles and philosophy can contribute to the improvement of three-dimensional models production for digital games. In software development, agile methods are widely used to manage projects and development teams. Such methods are led by the agile manifesto, prepared by leading industry professionals as a way to establish a pattern. The agile manifesto talk about people and interactions are more important than processes and tools. Software running is more important than comprehensive documentation and collaboration with the customer is more important than negotiating contracts. Responding to change is more important than following a plan. The manifesto sees clearly a trend towards appreciation of the person facing the process, project or product as it is the means of achieving these. The Agile Manifesto has its origin and source of inspiration in philosophy and agile principles of Lean, used by Toyota in its production system. It is estimated that for the development of specific agile good practice for the production of three-dimensional models for games provide an opportunity to work best in the industry, since with them we can find a pattern development. To get to list such practices, is sought in theoretical foundations of digital games, design and agile methods. A practical experiment, where it is an intersection of the data collected with an agile set of best practices for the development of three-dimensional models for environment digital games is displayed. As result, it is pointed out that agile practices contribute to the development of models since their understanding all the organizational levels. It infers that the understanding of the Lean philosophy applied area of digital games favor the understanding of which listed agile practices can be used in fact.