Thesis (M.S.)--University of Delaware, 2007. / Principal faculty advisor: Fouad Kiamilev, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 61-62).

Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g. 300-500mV) is a key technique to achieve high computing energy efficiency. It has enabled many new exciting applications in the field of Internet of Things (IoT) devices and energy-constrained applications such as medical implants, environment sensors, and micro-robots. Ultra-low-voltage (ULV) operation is also commonly used with the emerging architectures that are often non Von-Neumann style to empower energy-efficient cognitive computing. One the biggest challenge in realizing ULV design is the large circuit delay variability. To guarantee functionality in the worst-case process, voltage, and temperature (PVT) condition, the traditional safety margin approach requires operating at a slower clock frequency or higher supply voltage which significantly limits the achievable energy efficiency of the hardware. To fully claim the energy efficiency of ULV, the large circuit delay variation needs to be adaptively handled. However, the existing adaptive techniques that are optimized for nominal supply voltage operation and traditional Von-Neumann architectures become inefficient for ULV designs and emerging architectures. This thesis presents adaptive techniques based on timing error detection and correction (EDAC) that are more suitable for the energy-constrained ULV designs and the emerging architectures. The proposed techniques are demonstrated in three test chips: (1) R-Processor: A 0.4V resilient processor with a voltage-scalable and low-overhead in-situ EDAC technique. It achieves 38% energy efficiency improvement or 2.3X throughput improvement as compared to the traditional safety margin approach. (2) A 450mV timing-margin-free waveform sorter for brain computer interface (BCI) microsystem. It achieves 49.3% higher energy efficiency and 35.6% higher throughput than the traditional safety margin approach. (3) Ultra-low-power and robust power-management system which consists of a microprocessor employing ULV EDAC, 63-ratio integrated switched-capacitor DC-DC converter, and a fully-digital error based regulation controller. In this thesis, we also explore circuits for emerging techniques. The first is temperature sensors for dynamic-thermal-management (DTM). The modern high-performance microprocessors suffer from ever-increasing power densities which has led to reliability concerns and increased cooling costs from excessive heat. In order to monitor and manage the thermal behavior, DTM techniques embed multiple temperature sensors and use its information. The size, accuracy, and voltage-scalability of the sensor are critical for the performance of DTM. Therefore, we propose a temperature sensor that directly senses transistor threshold voltage and the test chip demonstrates 9X smaller area, 3X higher accuracy, and 200mV lower voltage scalability (down to 400mV) than the previous state-of-art. Another area of exploration is interconnect design for ultra-dynamic-voltage-scaling (UDVS) systems. UDVS has been proposed for applications that require both high performance and high energy efficiency. UDVS can provide peak performance with nominal supply voltage when work load is high. When work load is moderate or low, UDVS systems can switch to ULV operation for higher energy efficiency. One of the critical challenges for developing UDVS systems is the inflexibility in various circuit fabrics that are often optimized for a single supply voltage. One critical example is conventional repeater based long interconnects which suffers from non-optimal performance and energy efficiency in UDVS systems. Therefore, in this thesis, we propose a reconfigurable interconnect design based on regenerators and demonstrate near optimal performance and energy efficiency across the supply voltage of 0.3V and 1V.

Chim, Fu Shing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 79-82). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Background --- p.4 / Chapter 2.1 --- ATPG-Based Rewiring - REWIRE --- p.5 / Chapter 2.2 --- Graph-Based Rewiring - GBAW --- p.7 / Chapter 3 --- Characteristics of Rewiring Algorithms --- p.10 / Chapter 3.1 --- Comparsion between GBAW and REWIRE --- p.10 / Chapter 3.2 --- Problem Definition and Motivation --- p.11 / Chapter 4 --- Expanding Pattern Library --- p.14 / Chapter 4.1 --- Optimizing GBAW's Pattern Library --- p.14 / Chapter 4.2 --- Reduced Function Set for Gates within Patterns --- p.15 / Chapter 4.3 --- Rewiring with Multiple-Input Gates --- p.15 / Chapter 4.4 --- Experiment with GBAW Rewiring --- p.18 / Chapter 4.4.1 --- Experimental Results --- p.18 / Chapter 4.4.2 --- Discussion --- p.19 / Chapter 4.5 --- Experiment with Multi-way GBAW Partitioning --- p.21 / Chapter 4.5.1 --- Experimental Results --- p.22 / Chapter 4.5.2 --- Discussion --- p.24 / Chapter 4.6 --- Summary --- p.24 / Chapter 5 --- Circuit Structure for Rewiring --- p.26 / Chapter 5.1 --- Common Circuit Structure in GBAW Patterns --- p.26 / Chapter 5.2 --- Single Fanout Chains and Reconverging Alternative Wires for REWIRE --- p.28 / Chapter 5.3 --- Successive Rewiring --- p.31 / Chapter 5.4 --- Summary --- p.33 / Chapter 6 --- Chain-Based Rewiring Approach --- p.35 / Chapter 6.1 --- Single Fanout Chains in Graph-Based Rewiring --- p.35 / Chapter 6.2 --- Chain-Based Rewiring Approach --- p.36 / Chapter 6.3 --- Experimental Results --- p.40 / Chapter 6.4 --- Discussion --- p.41 / Chapter 6.5 --- Summary --- p.43 / Chapter 7 --- Hybrid Rewiring Framework --- p.44 / Chapter 7.1 --- Limit of Static Approaches --- p.44 / Chapter 7.2 --- Analyzing Framework of Dynamic Rewiring --- p.45 / Chapter 7.3 --- Techniques for Redundancy Identification --- p.47 / Chapter 8 --- Hybrid Chain-Based Rewiring Approach --- p.53 / Chapter 8.1 --- Hybrid Rewiring Framework --- p.53 / Chapter 8.1.1 --- Chain-Based Preliminary Target Wire Filtering --- p.55 / Chapter 8.1.2 --- Implication-Based Candidate Wire Generation --- p.55 / Chapter 8.1.3 --- Fast Redundancy Identification --- p.57 / Chapter 8.2 --- Uncontrollability and Controlling-Value Paths --- p.58 / Chapter 8.3 --- HYBRID - An Implementation of Our Framework --- p.61 / Chapter 8.4 --- Experimental Results --- p.63 / Chapter 8.5 --- Discussion --- p.65 / Chapter 8.6 --- Summary --- p.67 / Chapter 9 --- Rewiring Coupled FPGA Technology Mapping --- p.68 / Chapter 9.1 --- FPGA Technology Mapping --- p.68 / Chapter 9.2 --- Rewiring Coupled FPGA Technology Mapping --- p.70 / Chapter 9.2.1 --- Rewiring-based Logic Level Reduction --- p.71 / Chapter 9.2.2 --- Incremental Logic Resynthesis (ILR) Area Minimization --- p.71 / Chapter 9.3 --- Experimental Results --- p.72 / Chapter 9.4 --- Discussion --- p.73 / Chapter 9.5 --- Summary --- p.75 / Chapter 10 --- Conclusion and Future Works --- p.76 / Bibliography --- p.79

En los últimos años se ha producido un gran avance en el desarrollo de herramientas de diseño asistido por computador (cad) en microelectrónica, motivado en gran medida por la creciente complejidad de los circuitos integrados digitales. Este proceso ha incidido principalmente en la automatización del diseño desde el nivel lógico al layout, mientras que las etapas iniciales (especificación del algoritmo y determinación de la arquitectura) siguen dependiendo del diseñador. En la presente tesis se aborda el estudio, análisis e implementación de herramientas de síntesis de alto nivel, capaces de proponer la arquitectura del sistema digital que mejor implementa el comportamiento descrito a nivel algorítmico al tiempo que satisface una serie de restricciones impuestas por el diseñador. Los sistemas desarrollados, psal1 y psal2, parten de una descripción algorítmica en vhdl o isps y generan una arquitectura que describen en vhdl, cvs, bk o ddl, utilizando los algoritmos de síntesis de alto nivel propuestos en la tesis doctoral, la conexión de estas herramientas con sistemas de síntesis a nivel de transferencia de registros, permite disponer de una metodología de diseño automático desde el nivel algorítmico al layout.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 102-107). Available also in a digital version from Dissertation Abstracts.

As device geometries shrink, variability of process parameters becomes pronounced, resulting in a significant impact on the power and timing performance of integrated circuits. Deterministic optimization algorithms for power and area lack capabilities for handling uncertainty, and may lead to over-conservative solutions. As a result, there is an increasing need for statistical algorithms that can take into account the probabilistic nature of process parameters. Statistical optimization techniques however suffer from the limitation of high computational complexity. The objective of this work is to develop efficient algorithms for optimization of area and power under process variability while guaranteeing high yield. The first half of the dissertation focuses on two design-time techniques: (i) a gate sizing approach for area minimization under timing variability; (ii) an algorithm for total power minimization considering variability in timing and power. Design-time methods impose an overhead on each instance of the fabricated chip since they lack the ability to react to the actual conditions on the chip. In the second half of the dissertation we develop joint design-time and post-silicon co-optimization techniques which are superior to design-time only optimization methods. Specifically, we develop (i) a methodology for optimization of leakage power using design-time sizing and post silicon tuning using adaptive body bias; (ii) an optimization technique to minimize the total power of a buffer chain while considering the finite nature of adaptability afforded. The developed algorithms effectively improve the overconservatism of the corner-based deterministic algorithms and permit us to target a specified yield level accurately. As the magnitude of variability increases, it is expected that statistical algorithms will become increasingly important in future technology generations. / text

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Thesis (Ph. D.)--University of Hong Kong, 2009. / Includes bibliographical references (p. 90-98) Also available in print.