Linearity and efficiency are both critical parameters for radio frequency transmitter applications. In theory, a Doherty amplifier is a linear amplifier that is significantly more efficient than comparable conventional linear amplifiers. It comprises two amplifiers, connected at their outputs by a quarter-wave transformer. The main amplifier is always on, while the peaking amplifier is off during low power levels. Load modulation of the main amplifier occurs when the peaking amplifier is on due to the quarter-wave transformer, ensuring the main amplifier never enters saturation. This results in an efficiency characteristic that increases with respect to input power at twice the normal rate at low power levels, and plateaus to a high value at high power levels. However, in much of the research that has been done to-date, less-than-ideal results have been achieved (although efficiency was better than a conventional amplifier). It was decided to investigate the cause of the discrepancy between theoretical and practical results, and devise a method to counteract the problem. It was discovered that the main cause of the discrepancy was non-ideal transistor gate-voltage to drain-current characteristics. The implementation of a gate bias control scheme based upon measured transistor transfer characteristics, and the desired main and peaking amplifier output currents, resulted in a robust method to ensure near-ideal results. A prototype amplifier was constructed to test the control scheme, and theoretical, simulated and measured results were well matched. The amplifier had a region of high efficiency in the high power levels (over 34% for the last 6 dB of input power), and the gain was nearly constant with respect to input power (between 4 and 5 dB over the dynamic range). Furthermore, it was decided to investigate the role harmonics play within the Doherty amplifier. A classical implementation shunts unwanted harmonics to ground within the main and peaking amplifiers. However, odd harmonics generated by the peaking amplifier can be used to operate the main amplifier like a class F amplifier. This means its supply voltage can be lowered, without the amplifier entering saturation, and the efficiency of the Doherty amplifier can be increased without a detrimental effect on the its linearity. A prototype amplifier was constructed to test this theory, and gave good results, with better efficiency than that of a conventional amplifier, and a constant gain with respect to input power (between 6.4 dB and 6.5 dB over the dynamic range).

Modern wireless communication systems use spectrally efficient modulation schemes to reach high data rate transmission. These schemes are generally involved with signals with high peak-to-average power ratio (PAPR). Moreover, the development of next generation wireless communication systems requires the power amplifiers to operate over a wide frequency band or multiple frequency bands to support different applications. These wide-band and multi-band solutions will lead to reductions in both the size and cost of the whole system. This dissertation presents several advanced power amplifier solutions to provide wide-band and multi-band operations with efficiency improvement at power back-offs.

In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.

This work is focused on design of L band power amplifier. First, the design of the amplifier is substantiated by necessary theoretical basics of RF power amplifiers. Then, after comparsion of availible RF power amplifiers concepts, the doherty power amplifier is chosen as a suitable type. Design of the amplifier is focused on the linearity and efficiency. AWR design program is used for simulation of the amplifier. Amplifier is then realized and parameters are measured. Measured results are then discussed and evaluated. This work proposes design of the linear doherty amplifier for modern communications systems.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / A conventionally designed radio frequency amplifier operated in its linear region exhibits low DC to RF conversion efficiency. Typically, for a power amplifier designed for digital modulation applications, the amplifier is operated “backed-off” from its P1dB point by a factor of 10 or -10 dB. The typical linear amplifier is biased for either Class A or Class A/B operation depending on the acceptable design trade-offs between efficiency and linearity between these two methods. A novel design approach to increasing the efficiency of a linear RF power amplifier using a modified Odd-Way Doherty technique is presented in this paper. The design was simulated, built and then tested. The design yields improvements in efficiency and linearity.

This work explores the application of various power amplifier design techniques for mobile communications. Several circuit configurations including class A amplifier, Doherty amplifier and power combining amplifier have been developed, which are to improve the performance of power amplifiers in terms of power added efficiency transmission power and bandwidth. In chapter 2, the cascode PA adopting tuning capacitor structure is proposed and implemented to enhance the efficiency. In chapter 3, a novel Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is introduced. Moreover, the second harmonic cancellation function of balun combining PA is analysed and verified with experimental results in chapter 4. The fully integrated cascode class A amplifier adopts RC negative feedback, which is to enhance bandwidth and input/output matching. The integrated choke inductor compensating the parasitic capacitor of transistors has very low quality factor, which decreases the efficiency of the power amplifier. To reduce the inductance value of the choke inductor, a tuning capacitor is connected in parallel with the choke inductor. As a result, the inductor resistance is reduced as well, which diminishes the power consumption induced by the resistance of the choke inductor. This proposed PA configuration is validated by simulation results with the PAE improved by 3 % at the 1 dB compression point compared to the topology without tuning capacitor. The experimental results demonstrate a PA which delivers an output power of 21.3 dBm with PAE of 21 % at the 1 dB compression point. The Doherty amplifier with 2-way Wilkinson power splitter is integrated in a 0.9 mm×1.8 mm chip. The main and peak amplifier adopt cascode configuration to improve the stability of the Doherty amplifier. To minimize the chip size, the quarter wave transmission line in the topology is replaced by π-type lumped element equivalent network. To increase the operating bandwidth, the Doherty amplifier configuration using a 3-stage polyphase filter as power splitter is proposed. The topology consists of 3-stage RC polyphase filter, drive amplifiers, main amplifier, peak amplifier, and impedance inverter. By employing the polyphase filter, the quarter-wave transmission line at the input of the peak amplifier for compensating the phase shift of the impedance inverter is eliminated. According to the analysis of the polyphase filter prototype, the 3-stage polyphase filter is selected, and the component parameters are determined. The main amplifier and peak amplifier are using differential cascode configuration. The drive amplifier is to increase the power gain and provide proper impedance matching for the Doherty amplifier. The results demonstrate an outstanding broadband Doherty amplifier with a bandwidth of 1.8 GHz. The chip temperature rises dramatically due to the high power consumption of power amplifier. Consequently, the collector currents of the SiGe transistors are varying with the changing temperature, which deteriorates the PA performance. In the improved 3-stage PPF Doherty design, the bias voltages of the transistors in the first version 3-stage PPF Doherty amplifier are replaced by reference currents feeding through bias circuits. With current sources providing bias current to the transistors, the performance of the improved Doherty amplifier is enhanced. The power combining PAs are constructed on FR-4 PCB boards using discrete components. The single ended power amplifier in the power combining PA is built with high linearity HEMT transistor. The balun combining PA has an advantage of second harmonic cancellation, which is validated by both analysis and measurements. Moreover, power combining PAs with 2-way transmission line and lumped element Wilkinson power divider are designed. The transmission lines in these designs are analyzed using EM simulation tool and verified with testing structures on PCB boards.

Over the last decade, the number of mobile wireless devices on the market has increased substantially. New “multi-carrier” modulation schemes, such as OFDM, WCDMA, and WiMAX, have been developed to accommodate the increasing number of wireless subscribers and the demand for faster data rates within the limited commercial frequency spectrum. These complex modulation schemes create signals with high peak-to-average power ratios (PAPR), exhibiting rapid changes in the signal magnitude. To accommodate these high-PAPR signals, RF power amplifiers in mobile devices must operate under backed-off gain conditions, resulting in poor power efficiency. Various efficiency-enhancement solutions have been realized for backed-off devices to combat this issue. A brief overview of one of the more extensively researched solutions, the Doherty amplifier, is given, and its inherent limitations are discussed. A recently proposed amplifier topology that provides the efficiency benefits of the Doherty amplifier, while overcoming some of the fundamental problems that plague the standard Doherty architecture, is investigated. A step-by-step design methodology is presented and confirmed by extensive simulation in Agilent ADS. A design example, tuned for maximum efficiency at peak output power, is implemented on a PCB and tested to verify the validity of the proposed circuit configuration.