The power amplifiers are typically the most power-consuming block in wireless communication systems. Spectrum is expensive, and newer technologies demand transmission of maximum amount of data with minimum spectrum usage. This requires sophisticated modulation techniques, leading to wide, dynamic signals that require linear amplification. Although linear amplification is achievable, it always comes at the expense of efficiency. Most of the modern wireless applications such as WCDMA use non-constant envelope modulation techniques with a high peak to average ratio. Linearity being a critical issue, power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to overcome the battery lifetime limitation, a design of a high efficiency power amplifier that can maintain the efficiency for a wider range of radio frequency input signal is the obvious solution. A new technique that improves the drain efficiency of a linear power amplifier such as Class A or AB, for a wider range of output power, has been investigated in this research. The Doherty technique consists of two amplifiers in parallel; in such a way that the combination enhances the power added efficiency of the main amplifier at 6dB back off from the maximum output power. The classes of operation of power amplifier (A, AB, B, C etc), and the design techniques are presented. Design of a 2.14 GHz Doherty power amplifier has been provided in chapter 4. This technique shows a 15% increase in power added efficiency at 6 dB back off from the compression point. This PA can be implemented in WCDMA base station transmitter. / Master of Science

This thesis aims to implement a linear wireless transmitter based on the envelope-following architecture. A class-E PA is utilized to replace the linear PA used in the traditional envelope-following transmitter for enhancing the average efficiency. The transmitter relies on a digital processor realized by FPGA to generate the baseband IQ signal and corresponding envelope signal. This way can not only achieve more accurate modulation accuracy and wider modulation bandwidth, but also use less analog components for the future convenience of realizing single-chip integration when compared to the traditional envelope-following transmitter. Furthermore, this thesis implements a predistorter in the digital processor to compensate the Vdd/AM distortion of class-E amplifier. Therefore, this transmitter can simultaneously achieve high efficiency and high linearity over a wide input power range. From the results measured in transmitting a QPSK-modulated CDMA2000 1x signal at a chip rate of 1.2288 Mcps, the transmitter incorporating an InGaAs pHEMT class-E PA can achieve 30~44 % in average efficiency (23~38 % in average PAE) with above 44 dBc in ACPR and below 4 % in EVM in the average modulated output power range from 7 to 21 dBm, while the transmitter incorporating a GaAs HBT can achieve 20~40 % in average efficiency (16~35 % in average PAE) with above 43 dBc in ACPR and below 5 % in EVM in the average modulated output power range from 4 to 18.5 dBm.

Les signaux des nouveaux standard de communications (LTE) ont une grande différence entre la puissance maximale et moyenne (PAPR), cela n'est pas favorable pour l'utilisation dans les amplificateurs conventionnels vu qu'ils présentent un rendement maximale seulement quand ils travaillent au niveau de puissance maximale. Des amplificateurs de puissance Doherty pour présenter une efficacité constante pour une large gamme de puissance constituent une solution favorable à ce problème. Ce travail présente la méthodologie de conception et des résultats de mesure d'un amplificateur de puissance Doherty entièrement intégré dans la technologie 65 nm CMOS avec une constante PAE sur un 7 dB de plage de puissance. Mesures de 2,4 GHz à 2,6 GHz montrent des performances constantes PAE à partir du niveau de 20% jusqu'à 24% avec une puissance de sortie maximale de 23,4 dBm. Le circuit a été conçu avec une attention particulière pour le faible coût. / The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.

The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

No description available.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.