Simuladores quânticos têm tido um importante papel no estudo e desenvolvimento da computação quântica ao longo dos anos. A simulação de algoritmos quânticos em computadores clássicos é computacionalmente difícil, principalmente devido à natureza paralela dos sistemas quânticos. Para acelerar essas simulações, alguns trabalhos propõem usar hardware paralelo programável como FPGAs, o que diminui consideravelmente o tempo de execução. Contudo, essa abordagem tem três problemas principais: pouca escalabilidade, já que apenas transfere a complexidade do domínio do tempo para o domínio do espaço; a necessidade de re-síntese a cada mudança no algoritmo; e o esforço extra ao projetar o código RTL para simulação. Para lidar com esses problemas, uma arquitetura de um co-processador SIMD é proposta, cujas operações das portas quânticas está baseada no modelo Network of Butterflies. Com isso, eliminamos a necessidade de re-síntese com mudanças pequenas no algoritmo quântico simulado, e eliminamos a influência de um dos fatores que levam ao crescimento exponencial do uso de recursos da FPGA. Adicionamente, desenvolvemos uma ferramenta para geração automática do código RTL sintetizável do co-processador, reduzindo assim o esforço extra de projeto. / Quantum simulators have had a important role on the studying and development of quantum computing throughout the years. The simulation of quantum algorithms on classical computers is computationally hard, mainly due to the parallel nature of quantum systems. To speed up these simulations, some works have proposed to use programmable parallel hardware such as FPGAs, which considerably shorten the execution time. However this approach has three main problems: low scalability, since it only transfers the complexity from time domain to space domain; the need of re-synthesis on every change on the algorithm; and the extra effort on designing the RTL code for simulation. To handle these problems, an architecture of a SIMD co-processor is proposed, whose operations of quantum gates are based on Network of Butterflies model. Thus, we eliminate the need of re-synthesis on small changes on the simulated quantum algorithm, and we eliminated the influence of one of the factors that lead to the exponential growth on the consumption of FPGA resources. Aditionally, we developed a tool to automatically generate the synthesizable RTL code of the co-processor, thus reducing the extra design effort.

Simuladores quânticos têm tido um importante papel no estudo e desenvolvimento da computação quântica ao longo dos anos. A simulação de algoritmos quânticos em computadores clássicos é computacionalmente difícil, principalmente devido à natureza paralela dos sistemas quânticos. Para acelerar essas simulações, alguns trabalhos propõem usar hardware paralelo programável como FPGAs, o que diminui consideravelmente o tempo de execução. Contudo, essa abordagem tem três problemas principais: pouca escalabilidade, já que apenas transfere a complexidade do domínio do tempo para o domínio do espaço; a necessidade de re-síntese a cada mudança no algoritmo; e o esforço extra ao projetar o código RTL para simulação. Para lidar com esses problemas, uma arquitetura de um co-processador SIMD é proposta, cujas operações das portas quânticas está baseada no modelo Network of Butterflies. Com isso, eliminamos a necessidade de re-síntese com mudanças pequenas no algoritmo quântico simulado, e eliminamos a influência de um dos fatores que levam ao crescimento exponencial do uso de recursos da FPGA. Adicionamente, desenvolvemos uma ferramenta para geração automática do código RTL sintetizável do co-processador, reduzindo assim o esforço extra de projeto. / Quantum simulators have had a important role on the studying and development of quantum computing throughout the years. The simulation of quantum algorithms on classical computers is computationally hard, mainly due to the parallel nature of quantum systems. To speed up these simulations, some works have proposed to use programmable parallel hardware such as FPGAs, which considerably shorten the execution time. However this approach has three main problems: low scalability, since it only transfers the complexity from time domain to space domain; the need of re-synthesis on every change on the algorithm; and the extra effort on designing the RTL code for simulation. To handle these problems, an architecture of a SIMD co-processor is proposed, whose operations of quantum gates are based on Network of Butterflies model. Thus, we eliminate the need of re-synthesis on small changes on the simulated quantum algorithm, and we eliminated the influence of one of the factors that lead to the exponential growth on the consumption of FPGA resources. Aditionally, we developed a tool to automatically generate the synthesizable RTL code of the co-processor, thus reducing the extra design effort.

Simuladores quânticos têm tido um importante papel no estudo e desenvolvimento da computação quântica ao longo dos anos. A simulação de algoritmos quânticos em computadores clássicos é computacionalmente difícil, principalmente devido à natureza paralela dos sistemas quânticos. Para acelerar essas simulações, alguns trabalhos propõem usar hardware paralelo programável como FPGAs, o que diminui consideravelmente o tempo de execução. Contudo, essa abordagem tem três problemas principais: pouca escalabilidade, já que apenas transfere a complexidade do domínio do tempo para o domínio do espaço; a necessidade de re-síntese a cada mudança no algoritmo; e o esforço extra ao projetar o código RTL para simulação. Para lidar com esses problemas, uma arquitetura de um co-processador SIMD é proposta, cujas operações das portas quânticas está baseada no modelo Network of Butterflies. Com isso, eliminamos a necessidade de re-síntese com mudanças pequenas no algoritmo quântico simulado, e eliminamos a influência de um dos fatores que levam ao crescimento exponencial do uso de recursos da FPGA. Adicionamente, desenvolvemos uma ferramenta para geração automática do código RTL sintetizável do co-processador, reduzindo assim o esforço extra de projeto. / Quantum simulators have had a important role on the studying and development of quantum computing throughout the years. The simulation of quantum algorithms on classical computers is computationally hard, mainly due to the parallel nature of quantum systems. To speed up these simulations, some works have proposed to use programmable parallel hardware such as FPGAs, which considerably shorten the execution time. However this approach has three main problems: low scalability, since it only transfers the complexity from time domain to space domain; the need of re-synthesis on every change on the algorithm; and the extra effort on designing the RTL code for simulation. To handle these problems, an architecture of a SIMD co-processor is proposed, whose operations of quantum gates are based on Network of Butterflies model. Thus, we eliminate the need of re-synthesis on small changes on the simulated quantum algorithm, and we eliminated the influence of one of the factors that lead to the exponential growth on the consumption of FPGA resources. Aditionally, we developed a tool to automatically generate the synthesizable RTL code of the co-processor, thus reducing the extra design effort.

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.