Decision feedback equalization (DFE) is a sampled-data technique used for data recovery in digital communications channels. Multi-level decision feedback equalization (MDFE) has been developed for channels using the 2/3(1,7) RLL code. The optimum detector for a digital communication channel affected by ISI and noise consists of a matched filter, followed by a symbol rate sampler and a maximum likelihood sequence estimator. The optimal detector is unrealizable for saturation recording channels. A compromise structure uses fixed filter types with adjustable parameters. The objective is to maximize the signal-to-noise ratio in order to minimize the error rate. The read-channel waveform is corrupted at sampling instants by noise generated by various sources. We use a continuous-time low-pass filter cascaded with an all-pass filter at the receiver front-end. The low-pass filter band-limits high-frequency noise before sampling, and the all-pass filter equalizes the signal. This thesis examines different structures of the receiver and their optimal parameter placing. A design methodology developed specifically for choosing the poles and zeros location of the linear front-end part of the receiver is presented. It makes use of nonlinear optimization, and a software package written in MATLAB for equalizer computer aided design (CAD) is included in the appendix. The optimization criterion usually mentioned in the literature for digital channel optimal design is the sum of the intersymbol interference and noise. A new objective function is proposed in the thesis, and the error rate probability is shown to decrease by 30%. Issues pertaining to digital simulation of continuous-time systems are discussed. Design results are presented for different receiver structures, and bit error rate simulations are used for design validation. / Graduation date: 1997

Graduation date: 1995

Thesis (M. Dip. Tech. (Post School Education))--Peninsula Technikon, 1992. / Photocopy of original thesis. Bibliography: leaf 211-220. Also available online.

This thesis explores some new applications in power electronics for supercapacitors. This involves the design and development of dc-dc converters to interface the supercapacitor banks with the rest of the power electronic system. Two applications for supercapacitors are proposed and analyzed. The first application is aimed at high power applications such as motor drives. The proposed approach compensates the effect of voltage sags in the dc link of typical adjustable speed drives, thus reducing speed fluctuations in the motor and eliminating the possibility of nuisance tripping on the drive control board. The second approach presented in this thesis explores the use of supercapacitors to extend run-time for mobile devices such as laptop computers and hand held devices. Three possible approaches are explored: a) Supercapacitors connected directly across the battery; b) Battery-inductor-supercapacitor connection; and c) Supercapacitor, and battery connected via a DC-DC converter. Analytical models, simulation and experimental results on a typical laptop computer are presented.

Monolithic integration of optoelectronics on silicon is adream. This thesis deals with the studies on the heteroepitaxyof indium phosphide on silicon substrate towards making thatdream come true. Materials growth issues, characterization anddefect identification are addressed. Epitaxial lateral overgrowth (ELOG) technique is used togrow high quality epitaxial indium phosphide on a siliconsubstrate provided with a low quality indium phosphide seedlayer. Hydride vapor phase epitaxy is used for ELOG. The growthparameters were optimized first by carrying out ELOGexperiments on an InP substrate. The lateral growth rate isstrongly dependent on the orientation of the openings,thehighest growth rate being for the openings oriented at 30ºand 60º off [110]directions. But the vertical growth rateis relatively unaffected by the opening orientation. Theobservation of an inhomogeneous and orientation dependentdopant distribution within the same layer has been explained byinvoking the bonding configurations exposed to theincorporating dopant atoms in the different emergingplanes. When ELOG of InP is conducted on InP/Si, unlike that on InPsubstrates, the lateral growth is not symmetric on both sidesdue to the propagation of defects from the seed layer. Forexample, a higher concentration of threading dislocationsintersecting the surface of the {111}A emerging planes wouldcause a higher growth rate of these planes. The growth rate of{111}A planes with respect to the others can also be caused bythe vapor phase supersaturation as predicated byBurton-Cabrera-Frank model. The determined dislocation densityin the ELOG InP on InP/Si is ~ 4X107cm-2, which is nearly two magnitude lower than in theseed layer (~ 4X109cm-2). If the seed layer is of a better quality, theELOG layer will also be. Combination of high resolution x-raydiffraction reciprocal lattice mapping and low temperaturephotoluminescence indicates that the ELOG InP layer with highaspect ratio is nearly strain-free. When ELOG of sulfur doped InP is conducted on ring shapedopenings on InP/Si substrate instead of stripe openings,octahedral shaped ELOG InP templates with smooth surface areformed. Strain compensated InGaAsP 6 periods multi-quantumwells (MQW) at 1.5 μm wavelength (target value) were grownon these templates by metalorganic vapor phase epitaxy. RT-PLis indicative of a good quality ELOG layers. Optimized ELOG onring openings may become very attractive for heteroepitaxy ofIII-V compounds on silicon. As an extension of ELOG of InP on InP/Si, growth of InP isalso conducted on planar Focused-Ion-Beam (FIB)-modified (001)GaAs substrate. The impacts of the III/V ratio,crystallographic orientation of implanted lines andimplantation dose were explored. The choice of suitable growthconditions makes it possible to obtain continuous InP wiresaligned in all possible directions.

The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies. In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology. The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.

Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35μm HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.

Syftet med examensarbetet var att programmera en viterbiavkodare i VHDL och sedan syntetisera den till en FPGA. Först testades viterbialgoritmen i Matlab och Simulink för att få en förståelse för hur Viterbialgoritmen fungerar. Inom ramen för exjobbet har vi gjort en viterbiavkodare i Matlab samt en VHDL version som vi har simulerat i Modelsim. Avkodaren klarar inte av att avkoda punkterade bitströmmar. Att tillverka själva kodaren för punkterad kodning är enkelt men att sedan avkoda bitströmmen visade sig vara mer komplext. Att avkoda punkterad kod kräver ingen ändring av avkodaren men bitströmmen skall modifieras genom att man stoppar in dummybitar enligt ett givet mönster innan de når avkodaren men efter att mottagaren har tagit emot bitströmmen. Pga. tidsbrist prioriterades inte punkterad kodning och rapporten kom att ändra inriktning så att den snarare ska kunna fungera som starthjälp för kommande examensarbetare eller för andra inom universitetet som har till uppdrag att utveckla en viterbiavkodare.

This thesis presents a new family of converters for high power interconnection of dc buses with different voltage levels. Proposed converters achieve high voltage dc-dc conversion without an intermediate ac conversion stage. This function is implemented without series connection of active switches, or the use of isolation transformers. The salient features of proposed converters are (i) design and construction simplicity, (ii) low switching losses through soft turn-on and soft turn-off, (iii) single stage dc-dc conversion without high-current chopping, (iv) modular structure, (v) equal voltage sharing among the converter modules. Three converter circuits are investigated. The first performs unidirectional power transfer from a dc bus with higher voltage to a dc bus with lower voltage. The second performs unidirectional power transfer from a dc bus with lower voltage to a dc bus with higher voltage. Both converters are suitable for interconnecting single pole dc buses with same polarity, or double pole dc buses. A third converter is also presented which performs the function of either the first or the second converter with polarity reversal. The third converter is suitable for interconnecting single pole dc buses with different polarities, or double pole dc buses. By hybrid integration of the proposed three converters, the thesis also investigates other topologies for bidirectional power transfer between two dc buses. Proposed converters operate only in discontinuous conduction mode and exhibit soft switching operation for the active and passive switches. A common feature between the proposed converters is the self current turn-off for the active switches at zero voltage. This allows the use of thyristors as active switches alleviating their reverse recovery losses. For each converter topology, the structure is presented, its operation principle is explained and a complete set of design equations are derived. Comparisons are performed on high-power and high-voltage design examples. The merits and limitations of each converter are concluded. Practical considerations regarding components selection, loss analysis, filter design and the non-idealities of the circuits are studied. Experimental implementation of scaled-down laboratory prototypes is presented to provide a proof of concept and validate the operation principle of the proposed converter topologies.

Due to the lack of feedback networks, digital class D amplifiers operating in open loop typically have inferior performance when compared to analog class D amplifiers in closed loop configuration. This thesis presents an integrated distortion suppression circuit design for digital class D amplifiers, which forms a feedback loop around the output stage. This circuit suppresses the output stage distortion and noise by equalizing the modulator effective duty ratio and the output stage effective duty ratio. The suppression circuit is integrated with the class D modulator. An integrated class D amplifier output stage is implemented separately using a 0.35μm HV-CMOS technology. Experimental results confirm that the closed loop PSRR is improved by 15dB. The THD+N value is reduced by a factor of 2 to 30. The minimum THD+N is 0.03%, which is among the state of the art class D amplifiers.