Despite tremendous achievements, the field of conjugated polymers is still in its infancy, mimicking the more mature inorganic, i.e. silicon-based, technologies. We may though look forward to the realisation of electronic and electrochemical devices with exotic designs and device applications, as our knowledge about the fundamentals of these promising materials grow ever stronger. My own contribution to this development, originating from an idea first put forward by my tutor, Professor Magnus Berggren, is a design for a switchable polymer-based diode. Its architecture is based on a modified version of a recently developed highly-rectifying diode,12 where an intermediate molecular layer has been incorporated in the bottom contact. Due to its unique ability to switch its internal resistance during operation, this thin layer can be used to shift the amount of (forward) current induced into the rectifying structure of the device, and by doing so shift its electrical characteristics between an insulating and a rectifying behaviour (as illustrated below). Such a component should be of great commercial interest in display technologies since it would, at least hypothetically, be able to replace the transistors presently used to address the individual matrix elements. However, although fairly simple in theory, it proved to be quite the challenge to fabricate the device structure. Machinery errors and contact problems aside, several process routes needed to be evaluated and only a small fraction of the batches were successful. In fact, it was not until the very last day that I detected the first indications that the concept might actually work. Hence, several modifications might still be necessary to undertake in order to get the device to work properly.

This Master Thesis was conducted by Rikard Eriksson and Vlad Badea for their Master of Science degree in Electronics Design Engineering at the University of Linköping (Linköpings Universitet), Sweden. HTC Sweden AB initialized this Thesis and the Thesis contains a pre study of pseudolite based indoor navigation systems, a design of a simple pseudolite and finally some recommendations of applications. The pre study starts off with an introduction of the GPS system. This since pseudolite based systems and GPS have many similarities. Different pseudolites based techniques were then investigated and the pre study is wrapped up with a very short briefing on the Hammerhead chip. Some of the pseudolite based techniques were worth some more looking into and a pseudolite was therefore designed and simulated. There was unfortunate not enough time to actually build the pseudolite and verify it. Some recommendations to HTC Sweden were given in the last chapter of this thesis. The authors of this thesis recommend some interesting techniques and how the future work could proceed.

Multiprocessor architectures

Energy management system

<p>The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. </p><p>Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. </p><p>Next, a correlation-based signature analysis technique is presented for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging cost. Results are presented for a typical mixed-signal "big-D/small-A" SoC from industry, which contains a large section of flattened digital logic and several large mixed-signal cores.</p><p>Wafer-level test during burn-in (WLTBI) is an emerging practice in the semiconductor industry that allows testing to be performed simultaneously with burn-in at the wafer-level. However, the testing of multiple cores of a SoC in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. A test-scheduling technique is presented for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. </p><p>Finally, this thesis presents a test-pattern ordering technique for WLTBI. The objective here is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is solved using ILP and efficient heuristic techniques. The thesis also demonstrates how test-pattern manipulation and pattern-ordering can be combined for WLTBI. Test-pattern manipulation is carried out by carefully filling the don't-care (X) bits in test cubes. The X-fill problem is formulated and solved using an efficient polynomial-time algorithm. </p><p>In summary, this research is targeted at cost-efficient wafer-level test and burn-in of current- and next-generation semiconductor devices. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing cost-effective wafer-scale test solutions. The results of this research will lead to higher shipped-product quality, lower product cost, and pave the way for known good die (KGD) devices, especially for emerging technologies such as three-dimensional integrated circuits.</p> / Dissertation

<p>Microfluidics-based biochips combine electronics with biochemistry to open new application areas such as point-of-care medical diagnostics, on-chip DNA analysis, automated drug discovery and protein crystallization. Bioassays can be mapped to microfluidic arrays using synthesis tools and they can be executed through the electronic manipulation of sample and reagent droplets. The 2007 International Technology Roadmap for Semiconductors articulates the need for innovations in biochip and microfluidics as part of functional diversification ("Higher Value Systems" and "More than Moore"). This document also highlights "Medical" as being a System Driver for 2009 This thesis envisions an automated design flow for microfluidic biochips, in the same way as design automation revolutionized IC design in the 80s and 90s. Electronic design-automation techniques are leveraged whenever possible, and new design-automation solutions are developed for problems that are unique to digital microfluidics. Biochip users (e.g., chemists, nurses, doctors and clinicians) and the biotech/pharmaceutical industry will adapt more easily to new technology if appropriate design tools and in-system automation methods are made available. The thesis is focused on a design automation framework that addresses optimization problems related to layout, synthesis, droplet routing, testing, and testing for digital microfluidic biochips. Optimization goal includes the minimization of time-to-response, chip area, and test complexity. The emphasis here is on practical issues such as defects, fabrication cost, physical constraints, and application-driven design. To obtain robust, easy-to-route chip designs, a unified synthesis method has been developed to incorporate droplet routing and defect tolerance in architectural synthesis and physical design. It allows routing-aware architectural-level design choices and defect-tolerant physical design decisions to be made simultaneously. v In order to facilitate the manufacture of low-cost and disposable biochips, design methods that rely on a small number of control pins have also been developed. Three techniques have been introduced for the automated design of such pin-constraint biochips. First, a droplet-trace-based array partitioning method has been combined with an efficient pin assignment technique, referred to as the "Connect-5 algorithm". The second pin-constrained design method is based on the use of "rows" and "columns" to access electrodes. An efficient droplet manipulation method has been developed for this cross-referencing technique. The method maps the droplet-movement problem to the clique-partitioning problem from graph theory, and it allows simultaneous movement of a large number of droplets on a microfluidic array. The third pin-constrained design technique is referred to as broadcast-addressing. This method provides high throughput for bioassays and it reduces the number of control pins by identifying and connecting control pins with "compatible" actuation sequences. Dependability is another important attribute for microfluidic biochips, especially for safety-critical applications such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore, these devices must be adequately tested after manufacture and during bioassay operations. This thesis presents a cost-effective testing method, referred to as "parallel scan-like test", and a rapid diagnosis method based on test outcomes. The diagnosis outcome can be used for dynamic reconfiguration, such that faults can be easily avoided, thereby enhancing chip yield and defect tolerance. The concept of functional test for digital biochip has also been introduced for the first time in this thesis. Functional test methods address fundamental biochip operations such as droplet dispensing, droplet transportation, mixing, splitting, and capacitive sensing. To facilitate the application of the above testing methods and to increase their effectiveness, the concept of design-for-testability (DFT) for microfluidic biochips has been introduced in this thesis. A DFT method has been proposed that incorporates a test plan into vi the fluidic operations of a target bioassay protocol. The above optimization tools have been used for the design of a digital microfluidic biochip for protein crystallization, a commonly used technique to understand the structure of proteins. An efficient solution-preparation algorithm has been developed to generate a solution-preparation plan that lists the intermediate mixing steps needed to generate target solutions with the required concentrations. A multi-well high-throughput digital microfluidic biochip prototype for protein crystallization has also been designed. In summary, this thesis research has led to a set of practical design tools for digital microfluidics. A protein crystallization chip has been designed to highlight the benefits of this automated design flow. It is anticipated that additional biochip applications will also benefit from these optimization methods.</p> / Dissertation

Dissertation

Rapidly rising fossil fuel costs along with increased environmental awareness has encouraged the development of alternative energy sources. Such sources include fuel cells, wind, solar and ocean tide power. Among them, fuel cells have received increased interest in the recent years. This is mainly due to their high efficiency, modularity, and simple construction. However, due to their low output voltage and wide variation from no load to full load, a power electronics converter is required to interface the fuel cell with its loads. This dissertation focuses on developing a set of considerations that will assist designers of the power electronics converter in the design and optimization of the system. These design considerations are obtained analytically and verified experimentally and allow obtaining an efficient and stable fuel cell – power converter system. In addition to the design guidelines this dissertation presents new power converter topologies that do not require the use of transformers to achieve a large voltage gain. Further a new modular fuel cell power converter system that divides the fuel cell stack to optimize power generation is proposed. It is shown by means of mathematical analysis and experimental prototypes that the proposed solutions contribute to the reduction of size and cost of the power converter as well to increase the efficiency of the system.

China has become the most significant market in the world, since both the high demanding quantity and high potential in growth. China was ranked world wide number three for car sales and number two for car production volume in year 2007. In the meanwhile, according to the forecasting, China auto market will keeping in a growth rate higher than two digits in the coming five years. In contrast to the other major auto markets, USA, Europe and Japan, those markets are all keeping in low even minus sales growth cause from impacted by both the high gasoline price and economy depression. The purpose of this thesis is trying to fig out the competitive strategy and growth model for the Taiwan based automotive suppliers who already became China auto¡¦s supplier. Those suppliers have a very tough situation in China, due to them not only must face the giant global tier one but also the aggressively local based suppliers in China Auto market. The thesis will take the aspect of Taiwan based automotive suppliers, and probe into how those suppliers seeking the niche market and growth opportunity in such a severe market place. The specific objectives are: 1. Overview the Chinese automotive market and also predict the trend of such market. 2. Find the growth and also the competitive strategy for those suppliers. Through study the related thesis and publications, interview the insiders, analysis the row data/ industry survey reports and also combine with author¡¦s field experience in automotive, this thesis will come out below results: 1. General model for growth strategy. 2. The specific growth model for Taiwan based auto suppliers in China. 3. The competitive strategy for Taiwan based auto suppliers in China. 4. Suggestions for Chinese automotive suppliers.

<p>Monolithic integration of optoelectronics on silicon is adream. This thesis deals with the studies on the heteroepitaxyof indium phosphide on silicon substrate towards making thatdream come true. Materials growth issues, characterization anddefect identification are addressed.</p><p>Epitaxial lateral overgrowth (ELOG) technique is used togrow high quality epitaxial indium phosphide on a siliconsubstrate provided with a low quality indium phosphide seedlayer. Hydride vapor phase epitaxy is used for ELOG. The growthparameters were optimized first by carrying out ELOGexperiments on an InP substrate. The lateral growth rate isstrongly dependent on the orientation of the openings,thehighest growth rate being for the openings oriented at 30ºand 60º off [110]directions. But the vertical growth rateis relatively unaffected by the opening orientation. Theobservation of an inhomogeneous and orientation dependentdopant distribution within the same layer has been explained byinvoking the bonding configurations exposed to theincorporating dopant atoms in the different emergingplanes.</p><p>When ELOG of InP is conducted on InP/Si, unlike that on InPsubstrates, the lateral growth is not symmetric on both sidesdue to the propagation of defects from the seed layer. Forexample, a higher concentration of threading dislocationsintersecting the surface of the {111}A emerging planes wouldcause a higher growth rate of these planes. The growth rate of{111}A planes with respect to the others can also be caused bythe vapor phase supersaturation as predicated byBurton-Cabrera-Frank model. The determined dislocation densityin the ELOG InP on InP/Si is ~ 4X10⁷cm^-2, which is nearly two magnitude lower than in theseed layer (~ 4X10⁹cm^-2). If the seed layer is of a better quality, theELOG layer will also be. Combination of high resolution x-raydiffraction reciprocal lattice mapping and low temperaturephotoluminescence indicates that the ELOG InP layer with highaspect ratio is nearly strain-free.</p><p>When ELOG of sulfur doped InP is conducted on ring shapedopenings on InP/Si substrate instead of stripe openings,octahedral shaped ELOG InP templates with smooth surface areformed. Strain compensated InGaAsP 6 periods multi-quantumwells (MQW) at 1.5 μm wavelength (target value) were grownon these templates by metalorganic vapor phase epitaxy. RT-PLis indicative of a good quality ELOG layers. Optimized ELOG onring openings may become very attractive for heteroepitaxy ofIII-V compounds on silicon.</p><p>As an extension of ELOG of InP on InP/Si, growth of InP isalso conducted on planar Focused-Ion-Beam (FIB)-modified (001)GaAs substrate. The impacts of the III/V ratio,crystallographic orientation of implanted lines andimplantation dose were explored. The choice of suitable growthconditions makes it possible to obtain continuous InP wiresaligned in all possible directions.</p>