With the rapid growth of data communication infrastructure, there has been an increasing demand for multimedia communication services over the past years. This rapid growth has posed new requirements and challenges in many related research areas. This dissertation studies the problem of efficient and robust transmission of image and video contents over noisy channels. Firstly, joint source/channel coding algorithms are proposed for image transmission based on the new image coding standard JPEG2000. By combining the forward error correction capability provided by channel coding, together with the scalability and error resilience (ER) features provided by JPEG2000, the algorithm can achieve unequal error protection gains as well as robust source decoding for single image transmission over band-limited channels. Secondly, joint source/channel coding algorithms for multiple sources transmission over a common channel sharing a given total bandwidth are proposed. The algorithms exploit the rate-distortion diversity among multiple sources to optimally distribute a total bit rate given by the channel. It is demonstrated that both improved quality and reduced quality variance can be achieved at the receiver by the proposed algorithms. Finally, a robust image transmission scheme is proposed for packet erasure channels. The algorithm is based on the ER functionalities provided by JPEG2000 for robust source decoding. Together with the proposed interleaving scheme, some erasures can be recovered without channel coding.

Two circuit model extractors for complex multilayer microelectronic packages based on the Partial Element Equivalent Circuit (PEEC) technique, namely University of Arizona Effective Package Inductance Calculator (UAEPIC) and University of Arizona Effective Package Inductance and Capacitance Calculator (UAEPIC²), have been developed. The first one, UAEPIC, is based on the magneto-quasistatic assumption where the displacement current effect on the derivation of the electromagnetic field integral equation is neglected and thus the dominant inductive effects are modeled in order to extract the RL equivalent model. The second one, UAEPIC², uses a more rigorous electromagnetic model that accounts for displacement (yet nonretarded) electromagnetic effects to extract the RLC equivalent model of the given microelectronic package. The development of electrical models of packages of high complexity requires the numerical solution of linear systems of several thousands of equations. This makes the development of a broadband equivalent circuit to include skin effect computationally expensive. To circumvent this difficulty, two model order reduction techniques have been utilized. The method of Asymptotic Waveform Evaluation (AWE) has been incorporated in UAEPIC, and the Passive Reduced-order Interconnect Macromodeling Algorithm (PRIMA) has been applied to UAEPIC². Applications of AWE and PRIMA provide orders of magnitude reduction in computation labor and lead to a direct multiport Y-matrix representation in terms of the poles and residues. In this form, and using a special algorithm, the multiport, frequency-dependent equivalent circuit of the package can be incorporated efficiently in a SPICE-like circuit simulator. This simulation capability facilitates rapid and accurate simulations for the analysis of noise generation and signal degradation such as delay, cross-talk, power and ground bounces, and Simultaneous Switching Noise (SSN) in the package.

One of the vital phases in the design flow of electronic artifacts is the phase called physical design. In this phase--which traditionally involves partitioning, placement and routing problems--circuit designs are transformed into layouts ready for fabrication. Whether designing PCBs, MCMs or even VLSI chips, a problem that frequently arises is that of knowing if the layout will be routable. This is a classical problem of predicting routability/wireability that has been known since the early days of physical design. Unfortunately, quantifying the 'real' routability is a difficult task and hence the average wirelength based on the number of intramodule connections has become a common measure of routability. At the other end of this overly simplified measure, people do the actual place and route steps to determine the routability. In search of a more realistic way of quantifying the routability, a new method for measuring routability/wireability is proposed for use in general area routing problems. It focuses on MCM and dense PCB designs but can be extended to any general area routing problem. The routability is measured by extending the counting method of Pascal's Triangle where the number of potential routes of each net in the design can be obtained precisely. The method has made it possible to evaluate the number of potential routes in the presence of arbitrary obstacles as well as the possible limitations on the number of vias/bends to use. The theoretical development of the new method has resulted in two main algorithms called the EPTM and FEPT. Testing on several MCM benchmarks confirms what was intuitively believed that routes with 4 or less vias/bends are sufficient for general area routing problems in MCMs. It also uncovered the fact that increasing the number of vias/bends in the routes doesn't always increase the potential of routability unless detours are introduced. Further testing on non-minimum rectilinear paths shows that detours do improve the routability when the number of vias/bends between detour points is 3 or greater.

Volumetric phase portraits are mathematical primitives that describe vector field topology in a concise representation surrounding included critical points using a set of coupled differential equations. Phase portraits are classified into one of seven canonical forms depending on the phase portrait eigenvalues, and Jordan form. In addition, the dynamic behavior of these models is defined in terms of their index and signature functions. Relevant volumetric linear and nonlinear phase portrait models for both compressible and incompressible flow are discussed and classified, including their allowable topologies and characteristics. Volumetric phase portrait models are a compact descriptor of smoothly varying vector fields and are used to analyze, compress, and reconstruct vector fields. In addition to their application to vector fields, linear and nonlinear volumetric phase portraits may be used effectively in digital video and volumetric images. Two methods for reconstructing a vector field from its component phase portraits are presented, depending on the complexity of the flow and its boundary behavior. The first method uses a weighted superposition of phase portraits surrounding internal critical points to reconstruct vector fields consisting of non-turbulent, continuous flow and containing a finite number of spatially isolated critical points. For vector fields that violate the necessary assumptions for superposition based reconstruction, a discontinuous block processing method is used. Phase portraits are robust descriptors of field topology and are insensitive to additive noise. Also, an octave tree decomposition and subsequent merge algorithm is presented that models field topology with appropriately scaled phase portrait models. Vector field compression is demonstrated at a compression ratio of 156:1. Other applications include digital video compression, digital video scene and shot transition detection, and volumetric image classifications.

In mixed-signal ICs that integrate complex digital circuits together with high-performance analog circuits, signal contamination caused by substrate coupling noise is a critical issue. Fast digital transients can produce noise harmful to the sensitive analog circuits. The noise can be coupled from noisy devices and interconnects into the common substrate and coupled into analog devices. This noise coupling mechanism poses serious challenges toward the signal integrity of the mixed-signal design. The final performance of the ICs signal integrity is heavily dependent on layout schemes and the effectiveness of using noise reduction techniques. A hierarchical substrate coupling noise modeling technique that uses a gate-level lumped parasitic circuit model (for digital circuit layout) and concurrent real-time stimulating waveforms has been developed. This hierarchical approach make the concurrent substrate coupling noise analysis feasible under the current computational resource limitation. The gate-level parasitic extraction can avoid the intensive computation needed by detailed source/drain level modeling technique while keeping a reasonable accuracy with respect to parasitics. The parasitic extraction is also a separate process from the substrate three-dimensional mesh generation process. Therefore, this modeling technique can be easily used for evaluation of different physical design schemes. An innovate active noise reduction method, using the noise cancellation mechanism during the physical design phase to reduce the substrate coupling noise contamination, has also been developed. The fundamental idea of this method is to use the reversely amplified noise to achieve a "virtual" ground for the substrate. The noise is sampled from the substrate and reversely amplified and then re-injected into the substrate, by this method, up to 90% of the original noise can be eliminated. The active substrate coupling noise reduction method has the merit that it can be used together with traditional noise reduction methods such as guard ring deployment. Several test chips have been designed and fabricated to demonstrate the effectiveness of the substrate modeling and reduction methods. In the results section of this dissertation, results from both SPICE-based simulation and measurement from MOSIS 1.2 micron test chips are presented and analyzed.

Accurate and efficient simulation of lossy, multi-conductor transmission lines that are terminated by nonlinear circuits is necessary to design high-performance electronic circuits and packages. In this work, theoretical and practical considerations of lossy line simulation are presented. Using delay differential equations, the class of systems with "bidirectional delay" is introduced. These systems can be partitioned such that the resulting subsystems are only linked via delayed variables. It is stated in the "decoupling theorem" that the subsystems can be solved independently for a time interval, which is not longer than the shortest time delay. Circuits that contain transmission lines are shown to form systems with bidirectional delay and, consequently, can be decoupled. Using concepts derived from waveform relaxation, the decoupling is exploited to reduce the computational effort required for transmission line simulation. Moreover, an efficient method for the approximation of lossy line characteristics by rational transfer functions is presented. The method employs nonlinear minimization techniques and yields function coefficients suitable for time-domain modeling. Furthermore, the exponential wave propagation function is represented in the time domain, and discrete-time convolution is employed to calculate the transmission line response. Also described is a filtering method which considerably improves the stability of the simulation, while the deviation in the simulation results is smaller than the local truncation error. In addition, implementation of the lossy line simulator "UAFLICS" is outlined, and practical applications demonstrate the significance of coupling and loss effects.

A three dimensional finite element method software package has been developed for solving electromagnetic vector fields in conducting, magnetic materials and has been applied in two dimensions to ferromagnetic filaments and in three dimensions to a sphere. The bulk of this dissertation describes the approach to formulating the problem, choosing a solution routine, developing a method of discretization, verifying the accuracy and characterizing the computational efficiency of the package. Spurious vector solutions, which arise in numerical approximations to three dimensional electromagnetic problems, were eliminated by using a node-based formulation, with modified vector wave equation to ensure that divergence free conditions are satisfied. Conjugate gradient, iterative quasi-minimal residual solver (QMR) with a non-zero matrix element storage scheme expedited computation and reduced memory requirements. An automatic mesh generator for hexahedral elements was developed for discretization. The two dimensional study continued earlier analytical and experimental work on induction heating of multi-filament ferromagnetic strands. The present results demonstrate that coupling between filaments does not occur in two dimensions and is, in fact, a three dimensional effect provided the filaments are not in electrical contact. Furthermore, the accuracy of the solution can be established quantitatively by a single parameter, the ratio of one side of the finite element to the electromagnetic skin (or penetration) depth. The three dimensional parametric study investigates the effects on power absorption patterns in the sphere as a function of conductivity and permeability. Primarily, this research demonstrates that these types of problems can be solved accurately. Finally, it is shown that while the discretization must extend completely throughout the sphere for non-magnetic, moderately lossy media (conductivity, σ∼ 1 S/m, relative permeability, μᵣ ∼1), it need only consist of a thin shell of about three skin depths thick for highly conducting magnetic materials. The core of this sphere can be replaced by a field free inner perfectly conducting sphere. While the problem of computing power absorption in ferromagnetic implants for hyperthermia, the motivation for this study, was not solved completely, the foundations have been laid. Dependence of power absorption upon size, shape, permeability and conductivity as well as interactions between filaments of finite length can be addressed with this beginning.

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Much work has been done on the problem of stochastic modeling for the evaluation of performance, dependability and performability properties of systems, but little attention has been given to the interplay between the model and the performance measure of interest. Our work addresses the problem of automatically constructing Markov processes tailored to the structure of the system and the nature of the performance measures of interest. To solve this problem, we have developed new techniques for detecting and exploiting symmetry in the model structure, new reward variable specification techniques, and new state-space construction procedures. We propose a new method for detecting and exploiting model symmetry in which (1) models retain the structure of the system, and (2) all symmetry inherent in the structure of the model can be detected and exploited for the purposes of state-space reduction. Then, we extend the array of performance measures that may be derived from a given system model by introducing a class of path-based reward variables, which allow rewards to be accumulated based on sequences of states and transitions. Finally, we describe a new reward variable specification formalism and state-space construction procedure for automatically computing the appropriate level of state-space reduction based on the nature of the reward variables and the structural symmetry in the system model.

The dissertation addresses several problems in the power optimization and power-delay tradeoffs in digital CMOS circuits. The work is organized according to the three main sources of power dissipation: Power dissipation due to switching (P(sc)), standby or leakage power (P(leak)) and short circuit power (P(sc)). First we present new, efficient and provably correct algorithms for minimizing the switching power in combinational and sequential CMOS logic circuits. The techniques are based on the addition and removal of redundancies at the logic level. The basic technique developed for combinational circuits is extended to sequential circuits. Results of experiments carried on large (thousands of logic gates) commerical circuits (of the PowerPC chip) will be presented. Power dissipation due to the short circuit current has received much less attention. For submicron MOSFETs, this can be comparable to the switching power. A new, and computationally tractable model for the short circuit current in CMOS inverters and more complex CMOS gates was developed. This model was verified using a commerical 0.25 μm CMOS library and device models. The problem of minimizing the standby power for deep submicron technology is also addressed. The standby power dissipation has often been ignored in the design of CMOS circuits since its contribution to the total power dissipation has been negligable. However as device dimensions and voltages are scaled down, the standby power can be of the same order of magnitude as the switching power. This is a serious problem of many portable devices as they are in standby mode for considerable periods of time. One approach to alleviate this problem is the use of dual threshold voltages. We developed several new algorithms that optimally assign one of two threshold voltages to CMOS gates so as to minimize the standby power without sacrificing performance. The new algorithms handle circuits of thousands of gates and it is shown that the standby power can be reduced by as much as an order of magnitude without any loss of performance.