The effect of the electrical field enhancement at the junction discontinuities and its impact on the on-state resistance of power semiconductor devices was investigated. A systematic analysis of the mechanisms behind the techniques that can be used for the edge termination in power semiconductor devices was performed. The influence of the passivation layer properties, such as effective interface charge and dielectric permittivity, on the devices with different edge terminations was analyzed using numerical simulation. A compact analytical expression for the optimal JTE dose was proposed for the first time. This expression has been numerically evaluated for different targeted values of the blocking voltage and the maximum electric field, always resulting in the optimal field distribution that does not require further optimization with 2-D device simulator. A compact set of rules for the optimal design of super-junction power devices was developed. Compact analytical expressions for the optimal dopings and dimensions of the devices employed the field compensation technique are derived and validated with the results of numerical simulations on practical device structures. A comparative experimental study of several approaches used for the edge termination in SiC power diodes and transistors was performed. The investigated techniques included the mesa termination, high-k termination, JTE, and the combination of JTE and field plate edge termination. The mesa edge termination was found to be the most promising among the techniques investigated in this work. This stand-along technique satisfied all the imposed requirements for the ?ideal? edge termination: performance, reproducibility (scalability), and cost-efficiency. First of all, it resulted in the maximum one-dimensional electric field (E1DMAX) at the main device junction equal to 2.4 MV/cm or 93% of the theoretical value of critical electric field in 4H-SiC. Secondly, the measured E1DMAX was found to be independent of the voltage blocking layer parameters that demonstrate the scalability of this technique. Lastly, the implementation of this technique does not require expensive fabrication steps, and along with an efficient use of the die area results in the low cost and high yield.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第22447号 / 工博第4708号 / 新制||工||1735(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 山田 啓文, 准教授 船戸 充 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Ce travail de thèse est consacré à la conception et à la fabrication de diodes JBS en carbure de silicium. Une première partie de ce travail a consisté à concevoir par simulation une protection périphérique de la diode la plus efficace possible en réduisant sa sensibilité à la technologie (charges dans l’oxyde et activation des dopants). L’impact de la géométrie de l’anode de la diode JBS sur le champ électrique maximum sous le contact Schottky en inverse et la résistance série de la diode à l’état passant a été étudié. Une nouvelle architecture de diode JBS, à base de tranchées implantées, a été proposée pour pallier les limitations liées aux faibles profondeurs d’implantation d’Al. Une deuxième partie de ce travail a concerné le développement de briques technologiques, indispensables à la fabrication de la diode JBS, tels que les contacts métalliques et la gravure. Enfin, la fabrication complète et la caractérisation électrique de diodes ont été réalisées afin de valider les éléments de conception et l’intégration des briques technologiques développées durant cette thèse. / This study was dedicated to the design and to the fabrication of SiC JBS diodes. The first part of this work includes the design of robust efficient edge termination of the diode with special care to its technology sensitivity. The impact of anode layout of JBS diode on the maximum electric field under Schottky contact and on the on-state resistance has been investigated. A new structure of JBS diode, trenched and implanted, has been proposed to overcome the low Al implantation depth. A second part of this work has been focused on the development of technological steps required for the fabrication of JBS diodes such as metal contact and SiC etching. Finally, full fabrication and electrical characterization of diodes have been carried out in order to validate the design and the integration of technological steps developed during this thesis work.

Der Graben-Gate-MOSFET ist eine herausragende Bauelementarchitektur unter den vertikalen Bauelementen auf GaN-Basis, die derzeit für die nächste Generation der Leistungselektronik untersucht werden. Ein niedriges Reststromniveau im Aus-Zustand bei hoher Drain-Spannung ist für vertikale Transistoren von großer Bedeutung, da es ein entscheidendes Merkmal für eine hohe Durchbruchspannung und Zuverlässigkeit der Bauelemente ist. Die Drain-Restströme im Aus-Zustand haben ihren Ursprung in verschiedenen Quellen im vertikalen Trench-Gate-MOSFET. Neben dem Trench-Gate-Modul können auch die Reststrompfade an der trockengeätzten Seitenwand des lateralen Kantenabschlusses erheblich zum Drain-Reststrom im Aus-Zustand beitragen. In diesem Bericht wird der Einfluss jedes relevanten Prozessschritts auf den Drain-Reststrom im Aus-Zustand anhand spezifischer Teststrukturen auf hochwertigem epitaktischem GaN-Material, welche den lateralen Kantenabschluss des MOSFETs nachbilden, untersucht. Die elektrische Charakterisierung zeigt die Empfindlichkeit des Reststroms gegenüber plasmabezogenen Prozessen. Es wird eine Technologie der Randterminierung vorgestellt, die zu einem niedrigen Reststrom führt und gleichzeitig dicke dielektrische Schichten aus plasma-unterstützter Abscheidung enthält, die für die Herstellung einer Feldplattenstruktur über dem Kantenabschluss vorgesehen sind. / The trench gate MOSFET represents a prominent device architecture among the GaN based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.