This paper defines a variable transfer function that is used to compensate for low frequency structural resonances in a turret so that stabilization of a closed loop servo system can be achieved. Three circuits for implementing this compensation are presented. They are: the feedforward three amplifier biquad, the summing four amplifier biquad, and the single amplifier biquad with pole-zero cancellation. Design equations allowing the engineer to go directly from the given transfer function to the actual component values are developed for each circuit. A comparison of the final circuit designs is also presented.

No description available.

Thesis (M.S.)--Ohio University, November, 1994. / Title from PDF t.p.

The purpose of this thesis is to present a mathematical model in which we describe the theoretical approximation of the elliptic filters. From this theoretical treatment, the transfer function and its magnitude, as well as its poles and zeros, were programmed in Turbo Pascal for AT&T and IBM (PC/XT/AT) personal computers and their compatibles. The program, PC-ELLIP, also calculates the element values for double terminated two-port networks. Source code is included.

Wong Chun Kit. / Thesis submitted in: October 2006. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 73-76). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background and Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.4 / Chapter 1.3 --- Contributions --- p.4 / Chapter 1.4 --- Thesis Outline --- p.5 / Chapter 2 --- Digital Signal Processing --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Discrete-time Signals and Systems --- p.7 / Chapter 2.2.1 --- Discrete-time Signals --- p.7 / Chapter 2.2.2 --- Discrete-time Signal Processing Systems --- p.9 / Chapter 2.2.3 --- Linear Time-Invariant (LTI) Systems --- p.10 / Chapter 2.3 --- Finite Impulse Response (FIR) Filters --- p.13 / Chapter 2.3.1 --- Introduction --- p.13 / Chapter 2.3.2 --- Windowing FIR Filter Design Method --- p.15 / Chapter 2.4 --- Infinite Impulse Response (IIR) Filters --- p.17 / Chapter 2.4.1 --- Introduction --- p.17 / Chapter 2.4.2 --- Bilinear Transform IIR Filter Design Method --- p.18 / Chapter 2.4.3 --- Spectral Transformations of IIR Filters --- p.22 / Chapter 2.5 --- Comparison on FIR and IIR Filters --- p.25 / Chapter 2.6 --- Digital Signal Resampling --- p.26 / Chapter 2.6.1 --- Introduction --- p.26 / Chapter 2.6.2 --- Resampling by Decimation --- p.26 / Chapter 2.6.3 --- Resampling by Interpolation --- p.28 / Chapter 2.6.4 --- Resampling by a Rational Factor --- p.29 / Chapter 2.7 --- Introduction to Dual Fixed-point (DFX) Representation --- p.30 / Chapter 2.8 --- Summary --- p.33 / Chapter 3 --- Lyon and Mead's Cochlea Model --- p.34 / Chapter 3.1 --- Introduction --- p.34 / Chapter 3.2 --- Digital Cochlea Model: Cascaded IIR Filters --- p.37 / Chapter 3.2.1 --- Introduction --- p.37 / Chapter 3.2.2 --- Bandwidth and Centre frequencies --- p.38 / Chapter 3.2.3 --- Zeros and Poles --- p.39 / Chapter 3.3 --- Modifications for Decimated Cochlea Model --- p.41 / Chapter 3.3.1 --- Introduction --- p.41 / Chapter 3.3.2 --- Aliasing Avoidance --- p.42 / Chapter 3.3.3 --- Coefficient Modification after Decimation --- p.43 / Chapter 3.4 --- Summary --- p.47 / Chapter 4 --- System Architecture --- p.48 / Chapter 4.1 --- Introduction --- p.48 / Chapter 4.2 --- Hardware Platform and CAD Tools --- p.48 / Chapter 4.3 --- Sequential Processing Electronic Cochlea --- p.51 / Chapter 4.3.1 --- Pipelining - An Interleaving Scheme --- p.53 / Chapter 4.3.2 --- Decimation in Sequential Processing Electronic Cochlea . --- p.54 / Chapter 4.3.3 --- Multiple Sequential Cores --- p.55 / Chapter 4.3.4 --- Architecture of the DFX Filter Computation Core --- p.55 / Chapter 4.4 --- Summary --- p.60 / Chapter 5 --- Experimental Results --- p.61 / Chapter 5.1 --- Introduction --- p.61 / Chapter 5.2 --- Testing Environment --- p.61 / Chapter 5.3 --- Performance of the Sequential Electronic Cochlea --- p.63 / Chapter 5.3.1 --- Comparisons --- p.63 / Chapter 5.4 --- Summary --- p.69 / Chapter 6 --- Conclusions --- p.70 / Chapter 6.1 --- Future Work --- p.72 / Bibliography --- p.73

Power quality has become an important concern to both electric utilities and end users due to the increased use of non-linear loads in modem power systems over the past decade. Nonlinear loads inject harmonics into the power system and thus may lead to poor power quality and lower power factor. Current and voltage harmonics can adversely affect the operation of sensitive devices. A common remedial solution to reduce the effects of harmonic distortion in a power system is filtering. Passive and active filters are two common types of harmonic filters. An active filter, in general, is a controllable current source that injects current at the same magnitude and opposite phase to that of the harmonic current. For this thesis work, a DSP-controlled active filter to cancel lower order (5th, 7th, 11th, and 13th) harmonics in a three-phase, three-wire power system is designed. The proposed active filter employs a series LC tank tuned to a high frequency, along with a pulse-width modulated (PWM) converter topology. The PWM control of the active filter is implemented in a TMS320F240 DSP. The DSP implementation enhances the performance of the filter in real-time and enables the filter to compensate for varying loads. Additionally, the use of DSP-control reduces the number of components and therefore reduces the cost and improves the reliability of the overall system. The uniqueness of the filter is in its ability to control each harmonic separately. A laboratory prototype of the proposed active filter has been built and tested to verify the performance of the active filter. / Graduation date: 2001

With the increased attention on high efficiency and energy savings, power electronic energy conversion equipment is increasingly incorporated in all levels of the power system. The drawback of such equipment is the generation of nonsinusoidal currents in the power distribution network due to the nonlinear operation. Harmonic currents may distort the line voltages and lead to several unwanted effects including equipment overheating, system failure, interference with communication systems, etc. In response to these concerns, this research presents an active filter for the cancellation of harmonic line current distortion. The active filter used in this research is connected in parallel with the nonlinear load and is designed for a three-phase three-wire industrial power system. The filter consists of a voltage source inverter connected through a coupling inductor to the terminals of the ac-source. The inverter is controlled via a space vector-pulse width modulation (SVPWM) algorithm that is generated using a digital signal processor (DSP). In order to reduce the distortion resulting from the switching nature of the active filter inverter, a switching ripple filter is connected in parallel. The control algorithm of the active filter is based on the rotating reference frame theory. For each harmonic which is to be cancelled, a corresponding synchronous reference frame is generated to extract the harmonic phase and magnitude. With this information, each harmonic current component can be separately controlled and the proposed algorithm can therefore compensate for hardware effects such as measuring delays and component transfer functions. For the extraction of the harmonic components, a finite impulse response filter is used in order to quickly react to changing load currents. An adapting algorithm is implemented to compensate for slowly varying system parameters. Simulations under varying load and transient conditions are performed. The results show nearly perfect cancellation performance for the proposed active filter control algorithm. / Graduation date: 2001

The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 152-167). Also available in electronic version.