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A COMPILER FOR COMPUTER HARDWARE EXPRESSED IN MODIFIED APLGentry, Michael Lee, 1942- January 1971 (has links)
No description available.
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Visualization feedback from informal specificationsThakar, Aniruddha 24 March 2009 (has links)
This thesis describes the design and implementation of a system called the Model Generator that graphically models digital system specifications expressed in English. This research is part of the ASPIN project which has a long-term goal of providing an automated system for digital system synthesis from informal specifications.
Because of the versatility of the English language, there can be more than one interpretation of specification sentences. So before these specifications are synthesized into formal models, it is necessary to obtain validation of their interpretation from the specification author. The specification sentences are mapped into a common knowledge representation, called conceptual graphs, by first parsing and then semantically analyzing them. The Model Generator then uses the conceptual graphs to generate a graphical model representing the meaning of the English specification sentence. This is done in two stages. First, the commands for drawing the icons used for the graphical representation are assembled by consulting an Interpretation Library and a conceptual type hierarchy. In the second stage, the icons used in the representation are displayed using an X-Windows interface. The Model Generator has been implemented in the C programming language under the X-Windows environment. / Master of Science
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Display of arbitrary subgraphs for HPCOM-generated networksSlipp, Walter Whitfield, 1964- January 1989 (has links)
Hardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.
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Hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnections.January 1994 (has links)
by Lo Wing-yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves vii-ix). / ABSTRACT --- p.i / LIST OF TABLES --- p.iv / LIST OF FIGURES --- p.v / Chapter 1. --- INTRODUCTION --- p.1 / Chapter 1.1 --- Traditional Design Prototyping --- p.1 / Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2 / Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5 / Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6 / Chapter 2. --- HARDWARE DESIGNS --- p.9 / Chapter 2.1 --- Bus Interconnection --- p.9 / Chapter 2.1.1 --- Fixed buses --- p.9 / Chapter 2.1.2 --- Programmable buses --- p.12 / Chapter 2.2 --- Architectural Features --- p.15 / Chapter 2.2.1 --- Field programmable gate array --- p.15 / Chapter 2.2.2 --- Microprocessor --- p.15 / Chapter 2.2.3 --- Memory --- p.16 / Chapter 2.2.4 --- Buffers --- p.18 / Chapter 3. --- SOFTWARE TOOLS --- p.20 / Chapter 3.1 --- Critical Path Analysis --- p.20 / Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21 / Chapter 3.1.2 --- Computation time --- p.21 / Chapter 3.2 --- Circuit Partitioning --- p.23 / Chapter 3.2.1 --- Partitioning algorithm --- p.24 / Chapter 3.2.2 --- Effects of partitioning --- p.36 / Chapter 3.2.3 --- Partitioning parameters --- p.38 / Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39 / Chapter 3.3 --- IO Assignments --- p.40 / Chapter 3.3.1 --- Connect 4 FPGAs --- p.40 / Chapter 3.3.2 --- Connect 3 FPGAs --- p.42 / Chapter 3.3.3 --- Connect 2 FPGAs --- p.44 / Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47 / Chapter 3.4 --- Other Tools --- p.48 / Chapter 4. --- STRUCTURE ANALYSIS --- p.49 / Chapter 5. --- RESULTS --- p.52 / Chapter 6. --- FUTURE DIRECTION --- p.73 / Chapter 6.1 --- Other Possible Configurations --- p.73 / Chapter 6.2 --- Programmable Interconnection --- p.73 / Chapter 6.3 --- Expandability of UPB --- p.74 / Chapter 7. --- CONCLUSION --- p.75 / BIBLIOGRAPHY --- p.vii / APPENDICES --- p.x
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Testing and fault detection in a Fault-Tolerant MultiprocessorMantz, Michael Roy January 1981 (has links)
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND AERO / Bibliography: leaves B1-B6. / by Michael Roy Mantz. / M.S.
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Naming and synchronization in a decentralized computer system.Reed, David Patrick, 1952- January 1979 (has links)
Thesis. 1979. Ph.D.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Bibliography: leaves 212-216. / Ph.D.
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Logic design using programmable logic devicesNguyen, Loc Bao 01 January 1988 (has links)
The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Schemes to reduce power in FPGA implementations of the advanced encryption standardVan Dyken, Jason Daniel, January 2007 (has links) (PDF)
Thesis (M.S. in computer engineering)--Washington State University, December 2007. / Includes bibliographical references (p. 82-83).
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The relationship between learners' goal orientation and their cognitive tool use and achievement in an interactive hypermedia environmentKatz, Heather Alicia. January 2001 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI/Dissertation Abstracts International.
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The relationship between learners' goal orientation and their cognitive tool use and achievement in an interactive hypermedia environmentKatz, Heather Alicia 21 March 2011 (has links)
Not available / text
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