Today’s digital communication systems perform data transfers at the rate of millions of bits per minute, with data errors in the order of l/6th error per day. This magnitude of errorless communication is now possible because of sophisticated error correcting codes. Many types of error codes are employed today in three distinct areas of digital data communication: human to computer; data source to computer; computer to computer; and intra-computer; we are concerned here with intra-computer communication. This research is primarily a mathematical study of error codes in general to explore the possibilities of each major type for the purpose of implementation in real systems. The author was inspired toward this goal by several people and self-feelings. The first, was a definite affinity toward orderliness and the logical sequence of formal mathematics. Secondly, the thrusting of being assigned to a work project where computer maintenance and where all types of errors became important. And, finally an advisor who believes in “practical things”. The original portion of this endeavor is to be found in the conclusions drawn from each group of mathematical facts disclosed in the research. The particular bend of the author toward the cost/reliability/ efficiency of the system was not the intent of the theoretical mathematicians who did the majority of the work quoted herein. The author's contribution was to draw these ideas and works together and to form the conclusions based upon his experience and training as an Engineer. The primary conclusion is that multi-residue systematic codes appear to be the best choice for implementation of all around error correction and general hardware configurations. This conclusion is within the constraints that were laid down in the introduction of the research; 1) to not increase the cost of hardware, 2) to maintain or improve the system reliability, and 3) to maintain or increase the processing speed.

Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization with respect to asynchronous circuits, and ties the results into the STA solution of USC. The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and light in power. They have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP circuits excellent candidates for modern many-core, concurrent network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a `single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, the results of this work will provide confidence in the correct operation of GasP circuits.

No description available.

No description available.

This paper demonstrates conversion of an analog filter into a digital filter using computer aided software. The filter design to be demonstrated is a common third order Butterworth filter. This paper is not an attempt to review all filter designs or applications, but rather the attempt is to give a detailed explanation of the steps required to design almost any digital filter. No knowledge of the Intel Series 210 microcomputer development system is assumed. The appendices contain introduction to the Series 210 system. Chapter I demonstrates the steps needed to design this filter without computer aid. Included are both analog and digital filter response characteristics. Chapter II supplemented with Appendix C demonstrates the computer aided filter design. Again, filter characteristics are included. Chapter III compares the results of Chapter I and II. Even though this paper attempts to be inclusive of most of the computer details, it should not be used in exclusion of the available Series 210 manuals.

A major portion of digital system malfunctions are due to the presence of temporary faults which are either intermittent or transient. An intermittent fault manifests itself at regular intervals, while a transient fault causes a temporary change in the state of the system without damaging any of the components. Transient faults are difficult to detect and isolate and hence become a source of major concern, especially in critical real-time applications. Since satellite systems are particularly susceptible to transient faults induced by the radiation environment, a satellite communications protocol model has been developed for experimental research purposes. The model implements the MlL-TD-1553B protocol, which dictates the modes of communication between several satellite systems. The model has been developed employing the structural and behavioral capabilities of the HILO simulation system. SEUs are injected into the protocol model and the effects on the program flow are investigated. A two-tier detection scheme employing the concept of Signature Analysis is developed. Performance evaluation of the detection mechanisms is carried out and the results are presented. / Master of Science / incomplete_metadata

Most existing fault tolerant systems employ some form of dynamic redundancy and can be considered to be incident driven. Their recovery mechanisms are triggered by the detection of a fault. This dissertation investigates an alternative approach to fault tolerant design where the redundant system restores itself periodically to correct errors before they build up to the point of system failure. It is shown that periodically self restoring systems can be designed to be tolerant of both transient (intermittent) and permanent hardware faults. Further, the reliability of such designs is not compromised by fault latency. The periodically self restoring redundant (PSRR) systems presented in this dissertation employ, in general, N computing units (CU's) operating redundantly in synchronization. The CU's communicate with each other periodically to restore units that may have failed due to transient faults. This restoration is initiated by an interrupt from an external (fault tolerant) clocking circuit. A reliability model for such systems is developed in terms of the number of CU's in the system, their failure rates and the frequency of system restoration. Both transient and permanent faults are considered. The model allows the estimation of system reliability and mean time to failure. A restoration algorithm for implementing the periodic restoration process in PSRR systems is also presented. Finally a design procedure is described that can be used for designing PSRR systems to meet desired reliability specifications. / Ph. D.

Beneath the facade of the applications code of a well-designed real-time embedded system lies intrinsic firmware that facilitates a fast and effective means of detecting and diagnosing inevitable hardware failures. These failures can encumber the availability of a system, and, consequently, an identification of the source of the malfunction is needed. It is shown that the number of possible origins of all manner of failures is immense. As a result, fault models are contrived to encompass prevalent hardware faults. Furthermore, the complexity is reduced by determining syndromes for particular circuitry and applying test vectors at a functional block level. Testing phases and philosophies together with standardisation policies are defined to ensure the compliance of system designers to the underlying principles of evaluating system integrity. The three testing phases of power-on self tests at system start up, on-line health monitoring and off-line diagnostics are designed to ensure that the inherent test firmware remains inconspicuous during normal applications. The prominence of the code is, however, apparent on the detection or diagnosis of a hardware failure. The authenticity of the theoretical models, standardisation policies and built-in test philosophies are illustrated by means of their application to an intricate real-time system. The architecture and the software design implementing the idealogies are described extensively. Standardisation policies, enhanced by the proposition of generic tests for common core components, are advocated at all hierarchical levels. The presentation of the integration of the hardware and software are aimed at portraying the moderately complex nature of the task of generating a set of built-in tests for a real-time embedded system. In spite of generic policies, the intricacies of the architecture are found to have a direct influence on software design decisions. It is thus concluded that the diagnostic objectives of the user requirements specification be lucidly expressed by both operational and maintenance personnel for all testing phases. Disparity may exist between the system designer and the end user in the understanding of the requirements specification defining the objectives of the diagnosis. It is thus essential for complete collaboration between the two parties throughout the development life cycle, but especially during the preliminary design phase. Thereafter, the designer would be able to decide on the sophistication of the system testing capabilities. / Thesis (M.Sc.)-University of Natal, Durban, 1991.

To regain operation of a Minuteman Missile guidance computer, a ferromagnetic film was sprayed onto a previously inoperable memory disk after the original coating was removed using paint remover. The coating was then polished down to provide a smooth and uniform film, 1'he permanent data required for the clock and sector channels was determined from an operable Minuteman computer. 1-his information was then recorded on the memory disk using the write heads which were part of the complete memory unit. Digital electronics using integrated circuits provided theand generated the recording data _or the memory write heads. A "memory check" program verified the uniformity of the repaired memory by alternately writing "0' s" and "1' s" on each bit location and then reading and comparing the numbers to "0's" and "l's".Ball State UniversityMuncie, IN 47306

Cyberhistory is a thesis presented at The University of Western Australia for the Degree of Master of Science. Computer history is its prime field of focus. Cyberhistory pursues four key themes in computer history. These are, gender, the notion of the periphery, access and the role of the proselytiser. Cyberhistory argues that, gender issues are significant to computer history, culture ascribes gender to computing, and culture has driven computer development as much as technological progress. Cyberhistory identifies significant factors in the progress of computer technology in the 20th century. Cyberhistory finds that, innovation can occur on the periphery, access to computers can liberate and lead to progress, key proselytisers have impacted the development of computing and computing has become decentralised due to a need for greater access to the information machine. Cyberhistory traces a symbolic journey from the industrial periphery to the centres of computing development during WWII, then out to a marginal computer centre and into the personal space of the room. From the room, Cyberhistory connects into cyberspace. Cyberhistory finds that, despite its chaos, the Internet can act like a sanctuary for those seeking to bring imagination and creativity to computing.