published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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Many military communications systems utilize frequency-hopped spread spectrum waveforms to protect against jamming and enemy detection. These waveforms may be subjected not only to intentional jamming but may also be unintentionally jammed by other communications signals. While some systems can overcome inband interference with more signal power, covert systems may be limited to small amounts of transmitted power. The objective of this thesis was to investigate a method for resolving a frequency-hopped signal embedded in interference waveforms. With exponential averaging in the frequency domain, the spectra of the interfering signals can be estimated as long as they are present over a period longer than that of the frequency-hopped signal. Certain FFT sizes and weights are more beneficial to achieving this estimate than others. The interference estimate can be used to extract the desired frequency-hopped signal through spectral division of the received signal with the estimate. This technique is designated as noise-normalization. Simulations in MATLAB demonstrate the use of the technique and show how the desired signal can be resolved.

Tang Siu Kei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 107-111). / Abstracts in English and Chinese. / Acknowledgements --- p.ii / Abstract --- p.iii / List of Figures --- p.xi / List of Tables --- p.xvi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1 / Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1 / Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4 / Chapter 1.3 --- Research Goal and Contribution --- p.6 / Chapter 1.4 --- Thesis Outline --- p.6 / Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8 / Chapter 2.1 --- Amplifier Gain --- p.8 / Chapter 2.2 --- Noise Factor --- p.9 / Chapter 2.3 --- Linearity --- p.11 / Chapter 2.3.1 --- 1-dB Compression Point --- p.13 / Chapter 2.3.2 --- Third-Order Intercept Point --- p.14 / Chapter 2.4 --- Return Loss --- p.16 / Chapter 2.5 --- Power Consumption --- p.18 / Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19 / Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21 / Chapter 3.1 --- Dual-Diode Circuitry --- p.22 / Chapter 3.1.1 --- Working Principle --- p.22 / Chapter 3.1.2 --- Drawbacks --- p.24 / Chapter 3.2 --- Shunt-Inductor Method --- p.25 / Chapter 3.2.1 --- Working Principle --- p.25 / Chapter 3.2.2 --- Drawbacks --- p.27 / Chapter 3.3 --- Common-Gate Input Stage Method --- p.28 / Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29 / Chapter 3.3.2 --- Competitiveness --- p.31 / Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32 / Chapter 4.1 --- Small-Signal Modeling --- p.33 / Chapter 4.2 --- Method of Input Termination --- p.33 / Chapter 4.2.1 --- Resistive Termination --- p.34 / Chapter 4.2.2 --- Shunt-Series Feedback --- p.34 / Chapter 4.2.3 --- l/gm Termination --- p.35 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.36 / Chapter 4.3 --- Method of Gain Enhancement --- p.38 / Chapter 4.3.1 --- Tuned Amplifier --- p.38 / Chapter 4.3.2 --- Multistage Amplifier --- p.40 / Chapter 4.4 --- Improvement of Reverse Isolation --- p.41 / Chapter 4.4.1 --- Common-Gate Amplifier --- p.41 / Chapter 4.4.2 --- Cascoded Amplifier --- p.42 / Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44 / Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44 / Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46 / Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49 / Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49 / Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52 / Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54 / Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55 / Chapter 6.2 --- Design of Two-Stage Architecture --- p.57 / Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57 / Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59 / Chapter 6.3 --- Stability Consideration --- p.61 / Chapter 6.4 --- Design of Matching Networks --- p.62 / Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64 / Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67 / Chapter Chapter 7 --- Layout Considerations --- p.70 / Chapter 7.1 --- MOS Transistor --- p.70 / Chapter 7.2 --- Capacitor --- p.72 / Chapter 7.3 --- Spiral Inductor --- p.74 / Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76 / Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79 / Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81 / Chapter Chapter 8 --- Measurement Results --- p.82 / Chapter 8.1 --- Experimental Setup --- p.82 / Chapter 8.1.1 --- Testing Circuit Board --- p.83 / Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84 / Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84 / Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85 / Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86 / Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87 / Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89 / Chapter 8.2.1 --- S-parameter Measurement --- p.90 / Chapter 8.2.2 --- Noise Figure Measurement --- p.91 / Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92 / Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93 / Chapter 8.2.5 --- HBM ESD Test --- p.94 / Chapter 8.2.6 --- Summary of Measurement Results --- p.95 / Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96 / Chapter 8.3.1 --- s-parameter Measurement --- p.97 / Chapter 8.3.2 --- Noise Figure Measurement --- p.98 / Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99 / Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100 / Chapter 8.3.5 --- HBM ESD Test --- p.101 / Chapter 8.3.6 --- Summary of Measurement Results --- p.102 / Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103 / Chapter Chapter 9 --- Conclusion and Future Work --- p.105 / Chapter 9.1 --- Conclusion --- p.105 / Chapter 9.2 --- Future Work --- p.106 / References --- p.107 / Author's Publications --- p.112

Random Telegraph Signal (RTS) noise is a random noise source defined by discrete and metastable changes in the magnitude of a signal. Though observed in a variety of physical processes, RTS is of particular interest to image sensor fabrication where progress in the suppression of other noise sources has elevated its noise contribution to the point of approaching the limiting noise source in scientific applications. There have been two basic physical sources of RTS noise reported in image sensors. The first involves a charge trap in the oxide layer of the source follower in a CMOS image sensor. The capture and emission of a charge changes the conductivity across the source follower, altering the signal level. The second RTS source in image sensors has been reported in CCD and CMOS architectures and involves some metastability in the structure of the device within the light collection area. A methodology is presented for the analysis of RTS noise. Utilizing wavelets, a time-based signal has white noise removed, while RTS transitions are preserved. This allows for the simple extraction of RTS parameters, which provide valuable insight into defects in semiconductor devices. The scheme is used to extract RTS transition amplitudes and time constants from radiation damaged CMOS image sensor pixels. Finally, the generation of ionizing radiation induced RTS centers is investigated and discussed. Surprisingly, the number of RTS centers does not scale linearly with absorbed dose, but instead follows a quadratic dependence. The implications and possible mechanisms behind the generation of these RTS centers are discussed.

Thesis (M.S.)--State University of New York at Binghamton, Department of Electrical and Computer Engineering, 2006. / Includes bibliographical references.

This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behavioral noise simulations compared with the HSPICE noise simulations is obtained. The macro model is written for a charge-pump phase-locked loop, but can be easily extended to other architectures. The simulations are completed using SpectreS in Cadence. The designer can use the model to estimate the jitter at the output of the PLL in a top-down design methodology or cross verify the performance of an existing chip in a bottom-up approach. / Graduation date: 2001

Graduation date: 2006 / Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion.

Nanostructures are nanometer scale structures (characteristic length less than 100 nm) such as nanowires, ultra-small junctions, etc. Since nanostructures are less stable, their characteristic volume is much smaller compared to defect sizes and their characteristic length is close to acoustical phonon wavelength. Moreover, because nanostructures include significantly fewer charge carriers than microscale structures, electronic noise in nanostructures is enhanced compared to microscale structures. Additionally, in microprocessors, due to the small gate capacitance and reduced noise margin (due to reduced supply voltage to keep the electrical field at a reasonable level), the electronic noise results in bit errors. On the other hand, the enhanced noise is useful for advanced sensing applications which are called fluctuation-enhanced sensing. In this dissertation, we first survey our earlier results about the limitation of noise posed on specific nano processors. Here, single electron logic is considered for voltage controlled logic with thermal excitations and generic shot noise is considered for current-controlled logic. Secondly, we discuss our recent results on the electronic noise in nanoscale sensors for SEnsing of Phage-Triggered Ion Cascade (SEPTIC, for instant bacterial detection) and for silicon nanowires for viral sensing. In the sensing of the phage-triggered ion cascade sensor, bacteriophage-infected bacteria release potassium ions and move randomly at the same time; therefore, electronic noise (i.e., stochastic signals) are generated. As an advanced model, the electrophoretic effect in the SEPTIC sensor is discussed. In the viral sensor, since the combination of the analyte and a specific receptor located at the surface of the silicon nanowire occurs randomly in space and time, a stochastic signal is obtained. A mathematical model for a pH silicon nanowire nanosensor is developed and the size quantization effect in the nanosensor is also discussed. The calculation results are in excellent agreement with the experimental results in the literature.

Thesis (Ph. D.)--Oregon State University, 2010. / Printout. Includes bibliographical references (leaves 74-75). Also available on the World Wide Web.