<p>  </p> <p>Heat pipes and vapor chambers are passive two-phase heat transport devices that are used for thermal management in electronics. The passive operation of a heat pipe is facilitated by capillary wicking of the working fluid through a porous wick, and thus is subject to an operational limit in terms of the maximum pressure head that the wick can provide. This operational limit, often termed as the capillary limit, is the maximum heat input at which the pressure drop in the wick is balanced by the maximum capillary pressure head; operating a heat pipe or a vapor chamber above the capillary limit at steady-state leads to dryout. It thus becomes important to predict the performance of heat pipes and vapor chambers and explore the parametric design space to provide guidelines for minimized thermal resistance while satisfying this capillary limit. An increasingly critical aspect is to predict the transient thermal response of vapor chambers. Moreover, heat pipes and vapor chambers are extensively being used in electronic systems where the power input is dictated by the end-user activity and is expected to even exceed the capillary limit for brief time intervals. Thus, it is imperative to understand the behavior of heat pipes and vapor chambers when operated at steady and transient heat loads above the capillary limit as dryout occurs. However, review of the literature on heat pipe performance characterization reveals that the regime of dryout operation has been virtually unexplored, and thus this thesis aims to fill this critical gap in understanding.</p> <p>The design for minimized thermal resistance of a vapor chamber or a heat pipe is guided by the relative contribution of thermal resistance due to conduction across the evaporator wick and the saturation temperature gradient in the vapor core. In the limit of very thin form factors, the contribution from the vapor core thermal resistance dominates the overall thermal resistance of the vapor chamber; recent work has focused on working fluid selection to minimize overall thermal resistance in this limit. However, the wick thermal resistance becomes increasingly significant as its thickness increases to support higher heat inputs while avoiding the capillary limit. A thermal resistance network model is thus utilized to investigate the importance of simultaneously considering the contributions of the wick and vapor core thermal resistances. A generalized approach is proposed for vapor chamber design which allows <em>simultaneous</em> selection of the working fluid and wick that provides minimum overall thermal resistance for a given geometry and operating condition. While the thermal resistance network model provides a convenient method for exploring the design space, it cannot be used to predict 3-D temperature fields in the vapor chamber. Moreover, such thermal resistance network models cannot predict transient performance and temperature evolution for a vapor chamber. Therefore, an easy-to-use approach is proposed for mapping of vapor chamber transport to the heat diffusion equation using a set of appropriately defined effective anisotropic thermophysical properties, thus allowing simulation of vapor chamber as a sold conduction block. This effective anisotropic properties approach is validated against a time-stepping analytical model and is shown to have good match for both spatial and transient temperature predictions.</p> <p>Moving the focus from steady-state and transient operation of vapor chambers, a comprehensive characterization of heat pipe operation above capillary limit is performed. Different user needs and device workloads can lead to highly transient heat loads which could exceed the notional capillary limit for brief time intervals. Experiments are performed to characterize the transient thermal response of a heat pipe subjected to heat input pulses of varying duration that exceed the capillary limit. Transient dryout events due to a wick pressure drop exceeding the maximum available capillary pressure can be detected from an analysis of the measured temperature signatures. It is discovered that under such transient heating conditions, a heat pipe can sustain heat loads higher than the steady-state capillary limit for brief periods of time without experiencing dryout. If the heating pulse is sufficiently long as to induce transient dryout, the heat pipe may experience an elevated steady-state temperature even after the heat load is reduced back to a level lower than the capillary limit. The steady-state heat load must then be reduced to a level much below the capillary limit to fully recover the original thermal resistance of the heat pipe. The recovery process of heat pipes is further investigated, and a mechanism is proposed for the thermal hysteresis observed in heat pipe performance after dryout. A model for <em>steady-state</em> heat pipe transport is developed based on the proposed mechanism to predict the parametric trends of thermal resistance following recovery from dryout-induced thermal hysteresis, and the model is mechanistically validated against experiments. The experimental characterization of the recovery process demonstrates the existence of a maximum hysteresis curve, which serves as the worst-case scenario for thermal hysteresis in heat pipe after dryout. Based on the learnings from the experimental characterization, a new procedure is introduced to experimentally characterize the steady-state dryout performance of a heat pipe.</p> <p>To recover the heat pipe performance under steady-state, it has been shown that the heat input needs to be lowered down or <em>throttled</em> significantly below the capillary limit. However, due to the highly transient nature of power dissipation from electronic devices, it becomes imperative to characterize heat pipe recovery from dryout under transient operations. Hence, power-throttling assisted recovery of heat pipe from dryout has been characterized under transient conditions. A minimum throttling time interval, defined as time-to-rewet, is identified to eliminate dryout induced thermal hysteresis using power throttling. Dependence of time-to-rewet on throttling power is explored, and guidelines are presented to advise the throttling need and choice of throttling power under transient conditions. </p> <p>The experimental characterization of heat pipe operation at pulse loads above the capillary limit and power throttling following the pulse load helped define the dryout and recovery performance of a heat pipe. Next, a physics-based model is developed to predict the heat pipe <em>transient</em> thermal response under dryout-inducing pulse load and power throttling assisted recovery. This novel model considers wick as a partially saturated media with spatially and temporally varying liquid saturation, and accounts for the effect of wick partial saturation in heat pipe transport. The model prediction are validated against experiments with commercial heat pipe samples, and it is shown that the model can accurately predict dryout and recovery characteristics, namely time-to-dryout, time-to-rewet, and dryout-induced thermal hysteresis, for heat pipes with a range of wick types, heat pipe lengths and pulse loads above the capillary limit. </p> <p>The work discussed in this thesis opens certain questions that are expected to guide further research in this area. First, the thermal hysteresis mechanism proposed could be further validated with direct visualization of the liquid in a vapor chamber. To achieve this, X-ray microscopy is proposed as a viable option for the imaging <em>in situ</em> wetting dynamics in a vapor chamber. Second, the model developed to predict the dryout and recovery characteristics of the heat pipe can be used to design heat pipe with improved performance under pulse loads and power throttling. Third, novel wick designs can be explored that utilize the understanding developed of governing mechanisms for recovery from dryout, and can eliminate thermal hysteresis at powers closer to capillary limit. Fourth, the modeling approach can be extended to predict dryout and recovery trends in vapor chamber since the heat transfer pathways in a vapor chamber are different than those of a heat pipe. Fifth, and lastly it was observed several times during experiments that some of the heat pipe samples would exhibit complete dryout (sudden catastrophic rise in temperature and thermal resistance at the point of dryout) whereas other samples would exhibit partial dryout (noticeable but small increase in thermal resistance at dryout) at operating powers just above the capillary limit. Exploring and explaining the cause of complete dryout, in particular, would be an extremely valuable contribution to the heat pipe research. </p> <p>The work discussed in this thesis has led to the comprehensive development of a functional and mechanistic understanding of heat pipe operation above the notional capillary limit. The experimental procedures developed in this work are utilized to characterize a heat pipe performance under dryout and recovery. The models based on the mechanistic understanding developed from experimental characterization of dryout and recovery operation of a heat pipe have been experimentally validated and are useful for predicting heat pipe performance under dryout-inducing pulse loads and power-throttling.   </p>

<p dir="ltr">With increasing power densities in electronic devices, effective thermal management has become an indispensable aspect of electronic systems design. Although phase change materials (PCMs) have been studied as a potential solution, their integration into microelectronic and high-power devices presents a significant challenge due to low thermal conductivity and lack of effective thermal pathways from the heat source to the heat sink. While much work has focused on integrating thermal storage into heat sinks, this dissertation instead investigates integrating PCMs between the heat source and the heat sink in different configurations. By placing the energy storage closer to the heat source, the thermal resistance is reduced, which improves the overall thermal performance of the device. Specifically, this work explores the efficacy of two approaches: (1) direct embedding of a PCM within the die for mobile electronics applications and (2) integration of an auxiliary composite PCM/copper thermal energy storage (TES) component in combination with active liquid cooling for high-power power electronics modules.</p><p><br></p><p dir="ltr">The first study explores die-level thermal management for microelectronics using PCMs. Silicon chips with PCM embedded within the die are modeled using ParaPower, a fast-analysis tool, and a genetic algorithm is used to efficiently optimize the distribution of high-conductivity silicon pathways and high thermal capacitance PCM zones. A thermal test vehicle (TTV) of a realistic microelectronics form factor with an embedded PCM layer is first designed, and a process is developed to fabricate such a TTV. This study is the first to successfully fabricate a TTV with fully encapsulated PCM and validate its thermal response across various operational scenarios. For temperature cycling tests (where the TTV temperature fluctuates between predetermined hot and cold setpoints), the embedded-PCM TTVs extend the operational time by up to 2.8x compared to a baseline all-silicon TTV. For duty cycling tests (with a fixed duration of the periodic heating pulses and off times), the embedded-PCM TTVs suppress the hotspot temperature rise by up to 14% and stabilize quasi-steady state temperature fluctuations by up to 65% through repeated PCM melting and solidification cycles. Thermal performance enhancements are observed even for high heat fluxes of ~65W/cm² . Specifically, a TTV with an embedded square-shaped PCM reservoir reduces temperature instability by an average of 40% across a range of cycle durations.</p><p><br></p><p dir="ltr">The second study investigates the effectiveness of different integration strategies for an auxiliary composite PCM/copper TES block integrated alongside a cold plate, for thermal management of high-power power electronics modules, specifically for electric vehicles. These systems are evaluated for realistic drive cycles of various driving intensities. Computational results indicate that this approach is most effective when the composite TES block is positioned directly above the heat-generating silicon carbide dies. This configuration excels at stabilizing transient temperature fluctuations and absorbing thermal shocks, achieving reductions of up to approximately ~33% compared to current thermal management techniques. This strategy is particularly effective for stop-and-go drive cycles characterized by high rates of acceleration and deceleration, low average driving speeds, and frequent stops, typical of driving schedules for public transport buses and mail delivery vehicles.</p><p><br></p><p dir="ltr">The results from both thermal management approaches demonstrate that the integration of a PCM cooling solution in close proximity to the heat source can significantly enhance its effectiveness by absorbing power bursts and limiting temperature instability via repeated melting and solidification. The contributions of this dissertation include the development of an effective optimization strategy for generating optimized PCM distributions, which reduces the maximum temperature and temperature oscillations in a device with significant computational efficiency. (The same optimization strategy can be applied to other thermal management design challenges.) Notably, TTVs of realistic microelectronics form factors with embedded PCM were designed, modeled, fabricated, and validated. With the PCM thermal buffers, the engineered solution demonstrated superior performance compared to a baseline all-silicon TTV. The second study into the integration of composite PCM/copper TES blocks into high-power power electronics modules established trade-offs between different architectures across various performance metrics, and highlighted its effectiveness for drive cycles with varying intensities. These findings offer an important contribution to the development of embedded thermal management techniques for electronic systems design, which will be critical for the advancement of next-generation microelectronics and high-power devices.</p>

<p dir="ltr"><i>The high heat fluxes generated in electronic devices must be effectively diffused through </i><i>the semiconductor substrate and packaging layers to avoid local, high-temperature “hotspots” </i><i>that govern long-term device reliability. In particular, advanced semiconductor packaging </i><i>trends toward thin form factor products increase the need for understanding and improving </i><i>in-plane conduction heat spreading in anisotropic materials. Furthermore, predicting thermal </i><i>transport in vertical stacks of thinned and bonded die hinges on accurately characterizing </i><i>unknown buried interfacial thermal resistances. The design of semiconductor thermal packaging </i><i>solutions is hence limited by the functionality and accuracy of metrology available </i><i>for thermal properties characterization of engineered anisotropic heat spreading materials </i><i>and buried interfaces. This work focuses on the development of two separate innovative </i><i>metrology techniques for characterizing in-plane thermal properties of both isotropic and </i><i>anisotropic materials, and the measurement of low thermal interfacial resistances embedded </i><i>in stacks of semiconductor substrates.</i></p><p dir="ltr"><i>In the first portion of this thesis, a new measurement technique is developed for characterizing </i><i>the isotropic and anisotropic in-plane thermal properties of thin films and sheets, </i><i>as an extension of the traditional Ångstrom method and other lock-in thermography techniques. </i><i>The measurement leverages non-contact infrared temperature mapping to quantify </i><i>the thermal response to laser-based periodic heating at the center of a suspended thin film </i><i>sample. This novel data extraction method does not require precise knowledge of the boundary </i><i>conditions. To validate the accuracy of this technique, numerical models are developed </i><i>to generate transient temperature profiles for hypothetical anisotropic materials with known </i><i>properties. The resultant temperature profiles are processed through a fitting algorithm to </i><i>extract the in-plane thermal conductivities, without the knowledge of the input properties </i><i>to the forward model. Across a wide range of in-plane thermal conductivities, these results </i><i>agree well with the input values. The limits of accuracy of this technique are identified based </i><i>on the experimental and sample parameters. Further, numerical simulations demonstrate </i><i>the accuracy of this technique for materials with thermal conductivities from 0.1 to 1000 W </i><i>m</i><i>−1 </i><i>K</i><i>−1</i><i>, and material thicknesses ranging from 0.1 to 10 mm. This technique effectively</i> <i>measures anisotropy ratios up to 1000:1. Data from multiple heating frequencies can be </i><i>combined to fit for a single set of thermal properties (independent of frequency), which improves </i><i>measurement sensitivity as the thermal penetration depth varies across frequencies. </i><i>The post-processing algorithm filters out regions within the laser absorber and heat sink to </i><i>eliminate regions in the sample domain with boundary effects. Based on these guidelines, </i><i>experiments demonstrate the accuracy of this measurement technique for a wide range of </i><i>known isotropic and anisotropic heat spreading materials across a thermal conductivity range </i><i>of 0.3 to 700 W m</i><i>−1 </i><i>K</i><i>−1</i><i>, and in-plane anisotropy ratios of 30:1. These steps contribute </i><i>towards standardization of this measurement technique, enabling the development and characterization </i><i>of engineered heat spreading materials with desired anisotropic properties for </i><i>various applications.</i></p><p dir="ltr"><i>The second portion of this thesis focuses on characterization of thermal resistances across </i><i>“buried” interfaces that are challenging to characterize in situ due to their low relative magnitude </i><i>and embedded depth within a material stack. In particular, we target characterization </i><i>of interfaces that are buried deeper than the thermal penetration depth of available transient </i><i>measurement techniques, such as thermoreflectance, but have low thermal resistances </i><i>that prohibit the use of steady-state techniques, such as the reference bar method, due to </i><i>the very high temperature gradients that would be necessary resolve the resistances, among </i><i>other sample preparation challenges. This work develops a technique for the non-destructive </i><i>characterization of such deeply buried interfaces having thermal contact resistances of the </i><i>order of 0.001 cm</i><i>2</i><i>K/W. Two different embodiments of the measurement approach are first </i><i>assessed before down-selecting to a single experimental implementation. The working principle </i><i>for both embodiments includes a combination of non-contact periodic heating and </i><i>thermal sensing to measure the transient temperature response of a two-layer stack of materials </i><i>with a bonded interface of unknown thermal resistance. The approaches aim to </i><i>eliminate the preparation requirement of cutting samples to investigate their temperature in </i><i>cross-section. In the first embodiment, the sample stack is heated periodically at the center </i><i>of the sample, and cooled at the periphery, to create a radial temperature gradient. The </i><i>second embodiment involves generating a one-dimensional temperature gradient across the </i><i>stack by periodic heating of one face and steady cooling of the other face. The corresponding </i><i>ing amplitude and phase delay of the temperature responses are used to fit for the thermal </i><i>interfacial resistance, assuming a time-periodic solution for the heat diffusion equation for </i><i>a system with periodic heating. Numerical models developed for both approaches simulate </i><i>the transient temperature profiles across a two-layer bonded silicon stack of known thermal </i><i>properties, and enable an assessment of both approaches. The one-dimensional (1D) gradient </i><i>approach is found to have higher sensitivity and measurable signal compared to the </i><i>radial spreading approach, at the same mean temperature of the sample. </i></p><p dir="ltr"><i>Based on this 1D gradient concept, an experimental facility is developed, which includes </i><i>a IR-transparent heat sink, laser-based heating, and two IR temperature sensors for noncontact </i><i>temperature measurement of both sides of the sample. The unique IR transparent </i><i>heat sink design allows for simultaneous cooling and non-contact temperature measurement </i><i>of the bottom surface of the sample. An inverse fitting method is developed to extract </i><i>the thermal resistances using the steady periodic temperature amplitude and phase delay </i><i>across the thickness of the material. Thermal data generated using numerical simulations, </i><i>along with the data fitting method, is first leveraged to validate the extracted thermal resistance </i><i>values for two-layer material systems with an bonded interface, as well as for the </i><i>thermal conductivity measurement of bulk materials without an interface. The data extraction </i><i>process is shown to accurately extract thermal contact resistances on the order of </i><i>0.0001 cm</i><i>2</i><i>K/W in silicon-based packages for interfaces that are a few millimeters from the </i><i>exposed surface. For bulk materials, this technique demonstrates accuracy in extracting </i><i>the thermal conductivity of a wide range of materials ranging from thermal insulators to </i><i>highly conductive materials, spanning a range of 0.1 to 2000 W m</i><i>−1 </i><i>K</i><i>−1</i><i>. Physical measurements </i><i>of thermal conductivity of bulk silicon nitride and zinc oxide agree well with expected </i><i>reference values, and these measurements also align well with data from independently performed </i><i>experiments on the same materials using an established ASTM D5470 standard, </i><i>thereby validating this new measurement technique experimentally. Two-layer dry-contact </i><i>stacks of these two materials demonstrate the extraction of the thermal resistance across </i><i>interfaces buried up to 2 mm from the exposed surface. This work contributes toward standardization </i><i>of this technique for measurement of thermal resistances with low magnitudes </i><i>and buried depths, which are commonly found in modern electronic packages, ranging from </i><i>near-junction epitaxial semiconductor films to interconnect layers in emerging die-to-die and </i><i>wafer hybrid bonding technologies.</i></p><p dir="ltr"><i>Ultimately, these measurement techniques of in-plane thermal conductivity measurement </i><i>of anisotropic materials and the interfacial contact resistance measurements across buried </i><i>interfaces offer an important contribution to the area of thermal metrology, and advance the </i><i>field of next-generation semiconductor packaging.</i></p>

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