<p>Cutting edge research problems require the use of complicated and computationally expensive computer models. I will present a practical overview of the design and analysis of computer experiments in high energy nuclear and astro phsyics. The aim of these experiments is to infer credible ranges for certain fundamental parameters of the underlying physical processes through the analysis of model output and experimental data.</p><p>To be truly useful computer models must be calibrated against experimental data. Gaining an understanding of the response of expensive models across the full range of inputs can be a slow and painful process. Gaussian Process emulators can be an efficient and informative surrogate for expensive computer models and prove to be an ideal mechanism for exploring the response of these models to variations in their inputs.</p><p>A sensitivity analysis can be performed on these model emulators to characterize and quantify the relationship between model input parameters and predicted observable properties. The result of this analysis provides the user with information about which parameters are most important and most likely to affect the prediction of a given observable. Sensitivity analysis allow us to identify what model parameters can be most efficiently constrained by the given observational data set.</p><p>In this thesis I describe a range of techniques for the calibration and exploration of the complex and expensive computer models so common in modern physics research. These statistical methods are illustrated with examples drawn from the fields of high energy nuclear physics and galaxy formation.</p> / Dissertation

Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια: Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4]. Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10]. Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες και τα σχεδιαστικά χαρακτηριστικά της αναπτυξιακής κάρτας DE2 της ALTERA καθώς και τεχνική απεικόνισης video με τη χρήση FPGA [3], [9], [14]. Στο τέταρτο κεφάλαιο αναλύεται η λειτουργία του πρώτου μεγάλου τμήματος του μικροεπεξεργαστή, της ALU. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [6], [12], [13]. Στο πέμπτο κεφάλαιο αναλύεται η λειτουργία του register file. Πρόκειται για το τμήμα των καταχωρητών, το οποίο είναι υπεύθυνο για την μεταφορά δεδομένων και την λειτουργία των διαύλων διευθύνσεων. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [11], [13], [14]. Στο έκτο κεφάλαιο αναλύεται η λειτουργία του τμήματος ελέγχου διακοπών. Πρόκειται για το τμήμα το οποίο εξυπηρετεί οποιαδήποτε αίτηση για διακοπή και το οποίο έχει οριστεί να είναι υπεύθυνο και για την σειριακή επικοινωνία. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [1], [12], [13]. Στο έβδομο κεφάλαιο γίνεται μια πρώτη απόπειρα σύνδεσης των τριών πρώτων μεγάλων τμημάτων του μικροεπεξεργαστή [12], [13]. Στο όγδοο κεφάλαιο αναλύεται η λειτουργία της control unit ως μονάδα ελέγχου και διαχείρισης των σημάτων ελέγχου του όλου κυκλώματος του μικροεπεξεργαστή. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [12], [13]. Στο ένατο κεφάλαιο παρουσιάζεται το κύκλωμα του μικροεπεξεργαστή μέσα από την σύνδεση των επιμέρους τμημάτων του. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [7], [12], [13]. Στο δέκατο κεφάλαιο παρουσιάζεται ο μικροπρογραμματισμός της microprogram ROM της control unit. Αναλύεται διεξοδικά η λειτουργία των σημάτων ελέγχου των τμημάτων του μικροεπεξεργαστή για την εκτέλεση κάθε μιας εντολής του 8085 [7], [12], [13]. Στο ενδέκατο κεφάλαιο γίνεται εξομοίωση ορισμένων προγραμμάτων για τον έλεγχο της ορθής λειτουργίας των εντολών και των σημάτων ελέγχου και εξόδου του μικροεπεξεργαστή 8085 [1], [12], [13]. Στο δωδέκατο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροεπεξεργαστή στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA [3], [14]. Τελειώνοντας θα ήθελα να ευχαριστήσω τον επιβλέποντα της προσπάθειας αυτής Αναπληρωτή Καθηγητή κ. Ευάγγελο Ζυγούρη, η καθοδήγηση του οποίου υπήρξε καθοριστική. / The purpose of this thesis is the design of an 8085 emulator in FPGAs using VHDL. The implementation was done with the simulation environment of ALTERA Quartus v7.2, using VHDL. The project is divided into 12 chapters: The first chapter refers to the 8085 microprocessor and it’s technical features [1], [2], [4]. The second chapter is a detailed presentation of the VHDL language [3], [10]. The third chapter presents DE2 development board of Altera. Capabilities and design features of DE2 board are presented and vga video display generation using FPGAs is explained [3], [9], [14]. The fourth chapter analyzes the operation of the first large section of the microprocessor, ALU. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [6], [12], [13]. The fifth chapter presents the operation of the register file. Register File is responsible for data transfer and operation of the address bus. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [11], [13], [14]. The sixth chapter presents microprocessor 's interrupts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [1], [12], [13]. The seventh chapter is a first attempt to link the first three major sections of the microprocessor [12], [13]. The eighth chapter presents the operation of the control unit. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [12], [13]. The ninth chapter presents the circuit of the microprocessor through the connection of all individual parts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [7], [12], [13]. The tenth chapter presents the microprogramming of microprogram ROM of the control unit. It analyzes in detail the operation of the control signals of the parts of the microprocessor to perform each of 8085 command [7], [12], [13]. The eleventh chapter presents the simulation of microprocessor through assembly programs written in RAM memory of 8085 microprocessor [1], [12], [13]. The twelfth chapter presents the implementation of microprocessor in FPGAs using DE2 development board of Altera [3], [14].

Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2006-12-21Bitstream added on 2014-06-13T20:29:10Z : No. of bitstreams: 1 melo_ga_me_ilha.pdf: 6893159 bytes, checksum: a70518b6cdac1869ab5705bc69904150 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Este trabalho apresenta o desenvolvimento e implementação de um emulador para a característica estática de saída (Tensão versus Corrente) equivalente àquela de fontes de energia com células combustível. O emulador apresenta como vantagens, em relação à aquisição de uma FC, o baixo custo, o reduzido espaço físico e a flexibilidade via software para a implementação de diversas características baseadas em diferentes tipos de células combustível. Neste sentido, o emulador proposto permite a realização de ensaios preliminares durante a fase de projeto e os testes dinâmicos dos subsistemas de condicionamento de energia, sem a necessidade do acoplamento com o sistema de geração à células combustível, reduzindo-se os custos associados a estes testes laboratoriais. O emulador proposto consiste em um conversor Buck isolado Full-Bridge, com potência de saída de 2kW e alimentação via barramento de 400VCC, permitindo a emulação da característica nominal de saída de um conjunto de células tipo PEM (Proton Exchange Membrane - Membrana de Troca Protônica), em uma faixa de tensão de saída variando entre 32VCC e 72VCC, dependendo da corrente drenada pela carga. O circuito principal de controle é realizado através... / This work presents a design and implementation of an emulator to the static output characteristic (Voltage versus Current) that is similar to Fuel Cell generators. There are many advantages on using the Fuel Cell emulator. The emulator is cheaper, smaller and more flexible than the real Fuel Cell systems, because it is possible to emulate different characteristics through the use of a computer. In this context, a Fuel Cell emulator is proposed in this work in order to allow laboratory testes in the power conditioning system during its design and development stage. The proposed emulator is an insulated Full-Bridge converter with Buck operation, 2kW output power and 400VCC input voltage. This emulator achieves the output characteristic of a PEM (Proton Exchange Membrane) Fuel Cell stack with output voltage range of 32VCC to 72VCC, depending on the output current. The main control circuit is based on FPGA (Field Programmable Gate Array) and VHDL (Very High Speed Integrated Circuit Hardware Description Language) language. The experimental results demonstrate that the proposed emulator achieves the output static characteristic of the PEMFC Fuel Cell System and this output characteristic can be easily modified in order to obtain another desirable static... (Complete abstract click electronic access below)

Long Term Evolution (LTE) is the latest mobile network technology published by the Third Generation Partnership Project (3GPP). It might become a dominant technology for the next generation and it is attract-ing a great deal of attention from the top global corporations. IxLoad is a real-world traffic emulator, designed by the test solution provider Ixia. Mobile Packet Gateway (MPG) has been developed by Ericsson and is a commercial network equipment to provide a smart interface between mobile network (Global System for Mobile Communi-cation (GSM), Wideband Code Division Multiple Access (WCDMA), LTE) and internet for operators’ network. In this thesis, MPG is utilized to assess the capacity and LTE functionality of IxLoad. Capacity estima-tion will verify the maximum simulated users that can be supported by IxLoad and will test the maximum throughput IxLoad can achieve with a particular number of simulated users, under conditions involving a particular application scenario such as browsing HTTP. In addition to Session Management some other features such as Track Area Update and Handover, Busy Hour Functionality, Deep Packet Inspection, Mul-tiple Access Point Names (APNs) and Dynamic Quality of Service Enforcement are also covered in the functionality assessment. Moreover, this thesis gives a brief introduction to Evolved Packet Sys-tem (EPS), Evolved Packet Core (EPC), and to the functionality of MPG in addition to the role of MPG in EPS. Meanwhile the newest features of IxLoad are also presented in this document. Finally, as the outcome of this thesis, several suggestions are proposed in relation to improve-ments for IxLoad and MPG.

Les travaux de thèse concernent le développement d’une plateforme d’émulation temps réel destinée aux études théoriques et expérimentales des systèmes hybrides éolien- hydrolien. Diverses architectures de couplages énergétiques sont traitées sur la base des similitudes fonctionnelles des deux systèmes et par des concepts d’émulation à la fois numériques et expérimentaux. La notion de simulation en temps « accéléré » a été développée. Le concept a été validé sur la plateforme expérimentale en utilisant l’évolution de la puissance moyenne délivrée par une turbine éolienne de petite puissance. Cette approche pourra permettre de réduire les temps d’observation des campagnes de mesure, d’accélérer les études sur le potentiel éolien des sites en développement. Nous avons développé également deux types de couplage du système hybride éolien-hydolien. Un couplage électrique basé sur la connexion en parallèle sur un bus continu des deux turbines. Nous avons développé un concept innovant d’un couplage électromécanique basé sur l’utilisation d’une seule génératrice asynchrone sur laquelle sont simultanément couplés les arbres de la turbine éolienne et de la turbine hydrolienne. Pour cela, un servomoteur à commande vectorielle nous a servi à émuler la turbine éolienne pendant qu’un moteur synchrone nous a servi d'émulateur de turbine hydrolienne. L’arbre de la génératrice sert de couplage mécanique entre les deux systèmes. Nous avons mis en évidence dans les expérimentations effectuées, la complémentarité des productions électriques des deux systèmes, et également le besoin de leur adjoindre un système de stockage pour palier à une baisse simultanée de deux productions d’énergie. / The thesis work concerns the development of a real-time emulation platform for theoretical and experimental studies of offshore wind and tidal power hybrid systems. Various energy coupling architectures are processed on the basis of the functional similarities of two systems and by both numerical and experimental emulation concepts. The notion of accelerated time used for real time simulation has been developed. The concept was validated on the experimental platform using the evolution of the mean power delivered by a small wind turbine. This approach can reduce the observation times of the measurement campaigns and could accelerate the studies for the wind potential of developing sites. We have also developed two types of coupling of the wind-tidal hybrid system. An electrical coupling based on the connection in parallel on a continuous bus of two turbines. We have developed an innovative concept of an electromechanical coupling based on the use of a single asynchronous generator on which the wind turbine and tidal turbine are simultaneously coupled. For this purpose, a vector-controlled servomotor was used to emulate the wind turbine while a synchronous motor was used as a tidal turbine emulator. The generator shaft is used as a mechanical coupling between the two systems. We have demonstrated in the experiments that we have developed the complementarity of the electrical productions of the two systems; we highlighted the need to add a storage system to compensate the simultaneous decrease of the two energy productions. The real time simulations results allow us to validate the feasibility of such a coupling.

With the advent of virtualization and artificial intelligence, research on networked systems has progressed substantially. As the technology progresses, we expect a boom in not only the systems research but also in the network of systems domain. It is paramount that we understand and develop methodologies to connect and communicate among the plethora of devices and systems that exist today. One such area is mobile ad-hoc and space communication, which further complicates the task of networking due to myriad of environmental and physical conditions. Developing and testing such systems is an important step considering the large investment required to build such gigantic communication arrangements. We address two important aspects of network emulation in this work. We propose a network emulation framework, which emulates the functioning of a hierarchical software defined network. One such use-case is described using a mobile ad-hoc network (MANET) topology within a single system by leveraging contemporary network virtualization technologies. We present various aspects of the network, such as the dynamic communication in the software domain and provide a novel approach to build upon existing emulation techniques. The second part of the thesis presents a dynamic network link emulator. This emulator enables suitable link property re-configurations such as bandwidth, delay and packet loss for networked systems using simulation software. We characterize the results of tests for the link emulation using a hardware and software testbed. Through this thesis, we aim to make a small yet crucial contribution to the niche area of software defined networks.

This thesis is devoted to study the possibility of solving a hardware MISO emulator for fading channels and design of experimental device. The theoretical part starts with the theory of propagation of electromagnetic waves in a different types of environment, follows the principles and phenomena describing the radiocommunication channels and gradually gets up to specific channel models used for planning radio links. The actual design study of emulator is based on theoretical knowledge mentioned in this thesis. The basic principle of each channel model and thus so the emulator for fading channels is Tapped Delay Line model. From the point of view of the peripheral emulator solutions are designed with two topology circuits, parallel and serial-parallel. Emulator control method, mechanical arrangement, selection of topology circuit, components selection, desing of the PCB and software design is also analyzed. The results of this thesis is prototype production of experimental device and final discussion about achieved requirements and tasks.

This thesis deals with the design of external backscatter modulator for RFID tag emulator, which is used in UHF band. This modulator is connected with the Universal Software Radio Peripheral and antenna. Realization of a backscatter modulation contains switching between a matched load and an unmatched load. Impedance of the unmatched load is continuously adjustable. Result of this thesis is function prototype.

Auch eingefleischte LINUX-Nutzer bekommen mal eine eMail mit Wordanhang oder eine Coreldrawgrafik. Um Dokumente dieser Art anschauen zu können bleibt oft kein anderer Ausweg, als Windows zu booten. VMware bietet eine elegante Möglichkeit, mehrere Betriebssysteme auf einer Maschine gleichzeitig nutzen zu können. Natürlich sind dem Einsatz von VMware kaum Grenzen gesetzt.

Die PDAs von Palm Inc. und seinen Lizenznehmern werden gerne zur Adress- und Terminverwaltung eingesetzt. Damit ist ihr Leistungspotential jedoch nicht erschöpft. Wer gerne selbst Applikationen für Palm PDAs entwickeln möchte, ist dabei nicht zwingend auf eine windowsbasierte Entwicklungsumgebung angewiesen. Unter Linux gibt es Compiler, Ressourceeditoren und Emulatoren für PalmOS. Ich werde in meinem Vortrag diese Werkzeuge vorstellen, demonstrieren und ein Beispielprogramm zeigen.