Esta dissertação de mestrado propõe uma hierarquia de memória para a Estimação de Movimento e de Disparidade (ME/DE) centrada nas referências da codificação, estratégia chamada de Reference-Centered Data Reuse (RCDR), com foco em redução de energia em codificadores de vídeo multivistas (MVC - Multiview Video Coding). Nos codificadores MVC, a ME/DE é responsável por praticamente 98% do consumo total de energia. Além disso, até 90% desta energia está relacionada com a memória do codificador: (a) acessos à memória externa para a busca das referências da ME/DE (45%) e (b) memória interna (cache) para manter armazenadas as amostras da área de busca e enviá-las para serem processadas pela ME/DE (45%). O principal objetivo deste trabalho é minimizar de maneira conjunta a energia consumida pelo módulo de ME/DE com relação às memórias externa e interna necessárias para a codificação MVC. A hierarquia de memória é composta por uma memória interna (a qual armazena a área de busca inteira), um controle dinâmico para a estratégia de power-gating da memória interna e um compressor de resultados parciais. Um controle de buscas foi proposto para explorar o comportamento da busca com o objetivo de atingir ainda mais reduções de energia. Além disso, este trabalho também agrega à hierarquia de memória um compressor de quadros de referência de baixa complexidade. A estratégia RCDR provê reduções de até 68% no consumo de energia quando comparada com estratégias estadoda- arte que são centradas no bloco atual da codificação. O compressor de resultados parciais é capaz de reduzir em 52% a comunicação com memória externa necessária para o armazenamento desses elementos. Quando comparada a técnicas de reuso de dados que não acessam toda área de busca, a estratégia RCDR também atinge os melhores resultados em consumo de energia, visto que acessos regulares a memórias externas DDR são energeticamente mais eficientes. O compressor de quadros de referência reduz ainda mais o número de acessos a memória externa (2,6 vezes menos acessos), aliando isso a perdas insignificantes na eficiência da codificação MVC. A memória interna requerida pela estratégia RCDR é até 74% menor do que estratégias centradas no bloco atual, como Level C. Além disso, o controle dinâmico para a técnica de power-gating provê reduções de até 82% na energia estática, o que é o melhor resultado entre os trabalho relacionados. A energia dinâmica é tratada pela técnica de união dos blocos candidatos, atingindo ganhos de mais de 65%. Considerando as reduções de consumo de energia atingidas pelas técnicas propostas neste trabalho, conclui-se que o sistema de hierarquia de memória proposto nesta dissertação atinge seu objetivo de atender às restrições impostas pela codificação MVC, no que se refere ao processamento do módulo de ME/DE. / This Master Thesis proposes a memory hierarchy for the Motion and Disparity Estimation (ME/DE) centered on the encoding references, called Reference-Centered Data Reuse (RCDR), focusing on energy reduction in the Multiview Video Coding (MVC). In the MVC encoders the ME/DE represents more than 98% of the overall energy consumption. Moreover, in the overall ME/DE energy, up to 90% is related to the memory issues, and only 10% is related to effective computation. The two items to be concerned with: (1) off-chip memory communication to fetch the reference samples (45%) and (2) on-chip memory to keep stored the search window samples and to send them to the ME/DE processing core (45%). The main goal of this work is to jointly minimize the on-chip and off-chip energy consumption in order to reduce the overall energy related to the ME/DE on MVC. The memory hierarchy is composed of an onchip video memory (which stores the entire search window), an on-chip memory gating control, and a partial results compressor. A search control unit is also proposed to exploit the search behavior to achieve further energy reduction. This work also aggregates to the memory hierarchy a low-complexity reference frame compressor. The experimental results proved that the proposed system accomplished the goal of the work of jointly minimizing the on-chip and off-chip energies. The RCDR provides off-chip energy savings of up to 68% when compared to state-of-the-art. the traditional MBcentered approach. The partial results compressor is able to reduce by 52% the off-chip memory communication to handle this RCDR penalty. When compared to techniques that do not access the entire search window, the proposed RCDR also achieve the best results in off-chip energy consumption due to the regular access pattern that allows lots of DDR burst reads (30% less off-chip energy consumption). Besides, the reference frame compressor is capable to improve by 2.6x the off-chip memory communication savings, along with negligible losses on MVC encoding performance. The on-chip video memory size required for the RCDR is up to 74% smaller than the MB-centered Level C approaches. On top of that, the power-gating control is capable to save 82% of leakage energy. The dynamic energy is treated due to the candidate merging technique, with savings of more than 65%. Due to the jointly off-chip communication and on-chip storage energy savings, the proposed memory hierarchy system is able to meet the MVC constraints for the ME/DE processing.

Abstract The development of wireless networks has provided the necessary conditions for several new applications. The emergence of the virtual and augmented reality and the Internet of things and during the era of social media and streaming services, various demands related to functionality and performance have been set for mobile and wearable devices. Meeting these demands is complicated due to minimal energy budgets, which are characteristic of embedded devices. Lately, the energy efficiency of devices has been addressed by increasing parallelism and the use of application-specific hardware resources. This has been hindered by hardware development as well as software development because the conventional development methods are based on the use of low-level abstractions and sequential programming paradigms. On the other hand, deployment of high-level design methods is slowed down because of final solutions that are too much compromised when energy efficiency and performance are considered. This doctoral thesis introduces a model-driven framework for the development of signal processing systems that facilitates hardware and software co-design. The design flow exploits an easily customizable, re-programmable and energy-efficient processor template. The proposed design flow enables tailoring of multiple heterogeneous processing elements and the connections between them to the demands of an application. Application software is described by using high-level dataflow models, which enable the automatic synthesis of parallel applications for different multicore hardware platforms and speed up design space exploration. Suitability of the proposed design flow is demonstrated by using three different applications from different signal processing domains. The experiments showed that raising the level of abstraction has only a minor impact on performance. Video processing algorithms are selected to be the main application area in this thesis. The thesis proposes tailored and reprogrammable energy-efficient processing elements for video coding algorithms. The solutions are based on the use of multiple processing elements by exploiting the pipeline parallelism of the application, which is characteristic of many signal processing algorithms. Performance, power and area metrics for the designed solutions have been obtained using post-layout simulation models. In terms of energy efficiency, the proposed programmable processors form a new compromise solution between fixed hardware accelerators and conventional embedded processors for video coding. / Tiivistelmä Langattomien verkkojen kehittyminen on luonut edellytykset useille uusille sovelluksille. Muiden muassa sosiaalisen media, suoratoistopalvelut, virtuaalitodellisuus ja esineiden internet asettavat kannettaville ja puettaville laitteille moninaisia toimintoihin, suorituskykyyn, energiankulutukseen ja fyysiseen muotoon liittyviä vaatimuksia. Yksi isoimmista haasteista on sulautettujen laitteiden energiankulutus. Laitteiden energiatehokkuutta on pyritty parantamaan rinnakkaislaskentaa ja räätälöityjä laskentaresursseja hyödyntämällä. Tämä puolestaan on vaikeuttanut niin laite- kuin sovelluskehitystä, koska laajassa käytössä olevat kehitystyökalut perustuvat matalan tason abstraktioihin ja hyödyntävät alun perin yksi ydinprosessoreille suunniteltuja ohjelmointikieliä. Korkean tason ja automatisoitujen kehitysmenetelmien käyttöönottoa on hidastanut aikaansaatujen järjestelmien puutteellinen suorituskyky ja laiteresurssien tehoton hyödyntäminen. Väitöskirja esittelee datavuopohjaiseen suunnitteluun perustuvan työkaluketjun, joka on tarkoitettu energiatehokkaiden signaalikäsittelyjärjestelmien toteuttamiseen. Työssä esiteltävä suunnitteluvuo pohjautuu laitteistoratkaisuissa räätälöitävään ja ohjelmoitavaan siirtoliipaistavaan prosessoritemplaattiin. Ehdotettu suunnitteluvuo mahdollistaa useiden heterogeenisten prosessoriytimien ja niiden välisten kytkentöjen räätälöimisen sovelluksien tarpeiden vaatimalla tavalla. Suunnitteluvuossa ohjelmistot kuvataan korkean tason datavuomallien avulla. Tämä mahdollistaa erityisesti rinnakkaista laskentaa sisältävän ohjelmiston automaattisen sovittamisen erilaisiin moniprosessorijärjestelmiin ja nopeuttaa erilaisten järjestelmätason ratkaisujen kartoittamista. Suunnitteluvuon käyttökelpoisuus osoitetaan käyttäen esimerkkinä kolmea eri signaalinkäsittelysovellusta. Tulokset osoittavat, että suunnittelumenetelmien abstraktiotasoa on mahdollista nostaa ilman merkittävää suorituskyvyn heikkenemistä. Väitöskirjan keskeinen sovellusalue on videonkoodaus. Työ esittelee videonkoodaukseen suunniteltuja energiatehokkaita ja uudelleenohjelmoitavia prosessoriytimiä. Ratkaisut perustuvat usean prosessoriytimen käyttämiseen hyödyntäen erityisesti videonkäsittelyalgoritmeille ominaista liukuhihnarinnakkaisuutta. Prosessorien virrankulutus, suorituskyky ja pinta-ala on analysoitu käyttämällä simulointimalleja, jotka huomioivat logiikkasolujen sijoittelun ja johdotuksen. Ehdotetut sovelluskohtaiset prosessoriratkaisut tarjoavat uuden energiatehokkaan kompromissiratkaisun tavanomaisten ohjelmoitavien prosessoreiden ja kiinteästi johdotettujen video-kiihdyttimien välille.

This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques. / Graduation date: 2012

In this thesis, we consider wireless ad hoc and sensor networks where energy matters. Indeed, sensor nodes are characterized by a small size, a low cost, an advanced communication technology, but also a limited amount of energy. This energy can be very expensive, difficult or even impossible to renew. Energy efficient strategies are required in such networks to maximize network lifetime. We distinguish four categories of strategies: 1. Energy efficient routing, 2. Node activity scheduling, 3. Topology control by tuning node transmission power and 4. Reduction of the volume of information transferred. Our contribution deals with energy efficient routing and node activity scheduling. For energy efficient routing, the idea consists in reducing the energy spent in the transmission of a packet from its source to its destination, while avoiding nodes with low residual energy. The solution we propose, called EOLSR, is based on the link state OLSR routing protocol. We show by simulation that this solution outperforms the solution that selects routes minimizing the end-to-end energy consumption, as well as the solution that builds routes based on node residual energy. We then show how we can improve the benefit of energy efficient routing using cross layering. Informa- tion provided by the MAC layer improves the reactivity of the routing protocol and the robustness of routes. Moreover, taking into account the specificities of some applications like data gathering allows the routing protocol to reduce its overhead by maintaining routes only to the sink nodes. Concerning node activity scheduling, since the sleep state is the least power consuming state, our aim is to schedule node state between sleeping and active to minimize energy consumption while ensuring network and application functionalities. We propose a solution, called SERENA, based on node coloring. The idea is to assign a color to each node, while using a small number of colors and ensuring that two nodes with the same color can transmit without interfering. This color is mapped into a slot in which the node can transmit its messages. Consequently, each node is awake during its slot and the slots granted to its one-hop neighbors. It sleeps the remaining time. We show how this algorithm can adapt to different application requirements: broadcast, immediate acknowledgement of unicast transmissions... The impact of each additional requirement is evaluated by simulation. An originality of this work lies in taking into account real wireless propagation conditions. Color conflicts are then possible. A cross-layering approach with the MAC layer is used to solve these conflicts. We also show how cross-layering with the application layer can improve the coloring per- formance for data gathering applications. This work has been done for the ANR OCARI project whose aim is to design and implement a wireless sensor network for applications in harsh environments such as power plants and war- ships. The network layer including SERENA and EOLSR has been specified and is now under implementation.

Energy efficiency is a vital key component when designing and miniaturizing self sustained microsystems. The smaller the system, the smaller is the possibility to store enough stored energy for a long and continuous operational time. To move such a system in an energy efficient way, a piezoelectrical locomotion module consisting of four resonating cantilevers has been designed, manufactured and evaluated in this work. The combination of a suitable substrate, a multilayered piezoelectric material to reduce the voltage, and a resonating drive mechanism resulted in a low power demand. A manufacturing process for multilayer cantilever actuators made of P(VDF-TrFE) with aluminum electrodes on a substrate of flexible printed circuit board (FPC), has been developed. An important step in this process was the development of an etch recipe for dry etching the multilayer actuators in an inductive plasma equipment. Formulas for the quasi static tip deflection and resonance frequency of a multilayered cantilever, have been derived. Through theses, it was found that the multilayered structures should be deposited on the polymer side of the FPC in order to maximize the tip deflection. Both a large and a miniaturized locomotion module were manufactured and connected by wires to verify that the three legged motion principal worked to move the structures forward and backward, and turn it right and left. By touching and adding load, to a fourth miniaturized cantilever, its ability to act as a contact sensor and carry object was verified. The presented locomotion module is part of a multifunctional microsystem, intended to be energy efficient and powered by a solar panel with a total volume of less than 25 mm3 and weight 65 mg. The whole system, consisting of a solar cell, an infra red communication module, an integrated circuit for control, three capacitors for power regulating, the locomotion module and an FPC connecting the different modules, was surface mounted using a state of the art industrial facility. Two fully assembled systems could be programmed both through a test connector and through optical sensors in the multifunctional solar cell. One of these was folded together to the final configuration of a robot. However, the entire system could not be tested under full autonomous operating conditions. On the other hand, using wires, the locomotion module could be operated and used to move the entire system from a peak-to-peak voltage of 3.0 V.

Measuring the energy consumption of software components is a major building block for generating models that allow for energy-aware scheduling, accounting and budgeting. Current measurement techniques focus on coarse-grained measurements of application or system events. However, fine grain adjustments in particular in the operating-system kernel and in application-level servers require power profiles at the level of a single software function. Until recently, this appeared to be impossible due to the lacking fine grain resolution and high costs of measurement equipment. In this paper we report on our experience in using the Running Average Power Limit (RAPL) energy sensors available in recent Intel CPUs for measuring energy consumption of short code paths. We investigate the granularity at which RAPL measurements can be performed and discuss practical obstacles that occur when performing these measurements on complex modern CPUs. Furthermore, we demonstrate how to use the RAPL infrastructure to characterize the energy costs for decoding video slices.

Modern database systems have to process huge amounts of data and should provide results with low latency at the same time. To achieve this, data is nowadays typically hold completely in main memory, to benefit of its high bandwidth and low access latency that could never be reached with disks. Current in-memory databases are usually columnstores that exchange columns or vectors between operators and suffer from a high tuple reconstruction overhead. In this paper, we present the indexed table-at-a-time processing model that makes indexes the first-class citizen of the database system. The processing model comprises the concepts of intermediate indexed tables and cooperative operators, which make indexes the common data exchange format between plan operators. To keep the intermediate index materialization costs low, we employ optimized prefix trees that offer a balanced read/write performance. The indexed tableat-a-time processing model allows the efficient construction of composed operators like the multi-way-select-join-group. Such operators speed up the processing of complex OLAP queries so that our approach outperforms state-of-the-art in-memory databases.

We study energy-efficient power allocation among relays for lifetime maximization in a dual-hop relay network operated by amplify-and-forward relays with battery limitations. Power allocation algorithms are proposed for three different scenarios. First, we study the relay cooperation case where all the relays jointly support transmissions for a targeted data rate. By exploring the correlation of time-varying relay channels, we develop a prediction-based relay cooperation method for optimal power allocation strategy to improve the relay network lifetime over existing methods that do not predict the future channel state, or assume the current channel state remains static in the future. Next, we consider energy-efficient relay selection for the single source-destination case. Assuming finite transmission power levels, we propose a stochastic shortest path approach which gives the optimal relay selection decision to maximize the network lifetime. Due to the high computational complexity, a suboptimal prediction-based relay selection algorithm, directly coming from previous problem, is created. Finally, we extend our study to multiple source-destination case, where relay selection needs to be determined for each source-destination pair simultaneously. The network lifetime in the presence of multiple source-destination pairs is defined as the longest time when all source-destination pairs can maintain the target transmission rate. We design relay-to-destination mapping algorithms to prolong the network lifeii time. They all aim at maximizing the perceived network lifetime at the current time slot. The optimal max-min approach and suboptimal user-priority based approach are proposed with different levels of computational complexity. / UOIT

IEEE 802.15.4 is a standard designed for low data rate wireless personal area networks (WPANs) intended to provide connectivity to mobile devices. Such devices present considerable storage, energy, and communication constraints. However, they can be used in a variety of applications like home/office automation, environmental control and more. In order to extend the lifetime of the WPAN, we propose some changes to the standard including modifications to the Superframe Guaranteed Time Slot (GTS) distribution which can be optimized to reduce energy consumption. We implemented the proposed improvements to the IEEE 802.15.4 protocol using real sensor nodes. Specifically, we conducted an energy study of the proposed acknowledgment-based GTS descriptor distribution scheme and compared the results with the standard implementation. Experiments show that the proposed changes reduce energy consumption up to nearly 50% when 7 devices allocate guaranteed time slots descriptors during normal communication.

The proliferation of embedded systems, mobile devices, wireless sensor applications and in- creasing global demand for energy directed research attention toward self-sustainable and environmentally friendly systems. In the field of communications, this new trend pointed out the need for study of energy constrained communication and networking. Particularly, in the literature, energy efficient transmission schemes have been well studied for various cases. However, fundamental results have been obtained mostly for offline problems which are not applicable to practical implementations. In contrast, this thesis focuses on online counterparts of offline transmission scheduling problems and provides a theoretical background for energy efficient online transmission schemes. The proposed heuristics, Expected Threshold and Expected Water Level policies, promise an adequate solution which can adapt to short-time-scale dynamics while being computationally efficient.