O consumo de energia se torna cada vez mais importante para a arquitetura de processadores, onde o número de cores dentro de um mesmo chip está aumentando mas o total de energia disponível se mantém no mesmo nível ou até mesmo se reduz. Assim, técnicas para economizar energia, tais como opções de escala de frequência e desligamento automático de subsistemas, estão sendo usadas para manter a troca entre energia e desempenho. Para se obter alto desempenho, os atuais Chip Multiprocessors (CMPs) integram grandes memórias cache a fim de reduzir a latência média para acesso a memória principal, através da alocação do conjunto de dados da aplicação dentro do chip. Essas memórias cache tem sido projetadas tradicionalmente para explorar a localidade temporal usando políticas de substituição inteligentes e localidade espacial buscando todos os dados da linha da cache após uma falta de dados. Entretanto, estudos recentes mostraram que o número de sub-blocos dentro da linha da memória cache, que são realmente usados, costuma ser baixo, sendo que, os sub-blocos que são usados recebem poucos acessos antes de se tornarem mortos (isto é, nunca mais são acessados). Além disso, muitas da linhas da memória cache permanecem ligadas por longos períodos de tempo, mesmo que os dados não sejam usados novamente ou são inválidos. Para linhas de cache modificadas, a memória cache aguarda até que a linha seja expulsa para que esta seja gravada (write-back) de volta no próximo nível de memória. Essas escritas competem com as requisições de leitura (demanda do processador e prébusca da cache), aumentando a pressão no controlador de memória. Por essas razões, a eficiência energética e o desempenho das memórias cache não são ideais. Essa tese propõe a aplicação de preditores de uso de linhas da cache para aumentar a eficiência energética das memórias cache. São propostos os mecanismos Dead Sub-Block Predictor (DSBP) e Dead Line and Early Write-Back Predictor (DEWP) para permitir economia de energia sem que haja degradação do desempenho. DSBP é usado para prever quais sub-blocos da linha da cache serão usados e quantas vezes eles serão acessados de forma a trazer para a cache apenas os sub-blocos úteis e desliga-los após eles serem acessados pelo número de vezes previsto. DEWP prevê linhas de cache mortas assim que elas recebem o último acesso, desligando essas linhas. As linhas sujas são escalonadas para sofrerem write-back após a última operação de escrita, aumentando o potencial de salvar energia, reduzindo também a pressão no controlador de memória. Ambos os mecanismos propostos também reduzem a poluição nas memórias cache, dando prioridade para a expulsão de linhas mortas, melhorando as atuais políticas de substituição. Embora cada mecanismo apresentado seja capaz de funcionar separadamente dentro do sistema, ambos os mecanismos podem também ser misturados em uma mesma hierarquia de cache. Essa implementação mista é interessante pois a granularidade de sub-bloco é preferível para níveis de cache próximos do processador, onde as linhas de memória cache são expulsas rapidamente, enquanto o último nível de cache tende a usar toda a linha antes da sua expulsão. Com o intuito de avaliar os mecanismos propostos, é apresentado o Simulator of Non- Uniform Cache Architectures (SiNUCA). Esse simulador de microarquitetura com precisão de ciclos é validado em termos de desempenho e consumo de energia através da comparação com um processador real. Os resultados de desempenho foram obtidos executando aplicações das cargas de trabalho single-threaded do conjunto SPEC-CPU2006 e aplicações multi-threaded dos conjuntos SPEC-OMP2001 e NAS-NPB. Os resultados relativos a energia foram obtidos integrando o SiNUCA com as ferramentas de modelagem Multi-core Power, Area, and Timing (McPAT) e CACTI. Quando aplicados os mecanismos em todos os níveis de memória cache, observou-se em média uma redução de 36% no consumo de energia usando o DSBP, 25% usando o DEWP e 37% quando usou-se o DSBP nos níveis L1 e L2 e o DEWP no último nível. Todas essas reduções causaram uma perda desprezível de desempenho de menos de 4% em média. / Energy consumption is becoming more important for processor architectures, where the number of cores inside the chip is increasing and the total power budget is kept at the same level or even reduced. Thus, energy saving techniques such as frequency scaling options and automatic shutdown of sub-systems are being used to maintain the trade-off between power and performance. To deliver high performance, current Chip Multiprocessors (CMPs) integrate large caches in order to reduce the average memory access latency by allocating the applications’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality by using smart replacement policies, and spatial locality by fetching entire cache lines from memory on a cache miss. However, recent studies have shown that the number of sub-blocks within a line that are actually used is often low, and those sub-blocks that are used are accessed only a few times before becoming dead (that is, never accessed again). Additionally, many of the cache lines remain powered for a long period of time even if the data is not used again, or is invalid. For modified cache lines, the cache memory waits until the line is evicted to perform the write-back to next memory level. These write-backs compete with read requests (processor demand and cache prefetch), increasing the pressure on the memory controller. For these reasons, the energy efficiency and performance of cache memories are not ideal. This thesis introduces cache line usage predictors to increase the energy efficiency of cache memories. We propose the Dead Sub-Block Predictor (DSBP) and Dead Line and Early Write-Back Predictor (DEWP) mechanisms to enable energy savings without performance degradation. DSBP is used to predict which sub-blocks of a cache line will be actually accessed and how many times they will be used in order to bring into the cache only those sub-blocks that are necessary, and power them off after they are accessed the predicted number of times. DEWP predicts dead lines as soon as they receive the last access, and turns off these lines. Dirty lines are scheduled for write-back after the last write operation occurs, increasing the energy savings potential and also reducing the pressure on the memory controller. Both proposed mechanisms also reduce pollution in cache memories by prioritizing dead lines for eviction in the existing replacement policy. Although each introduced mechanism is capable of performing separately inside a system, both mechanisms can also be mixed in the same cache hierarchy. This mixed implementation is interesting because the sub-block granularity is more suitable for cache levels closer to the processor, where the cache lines are quickly evicted, while the Last- Level Cache (LLC) tends to use the whole cache line before its eviction. In order to evaluate our proposed mechanisms, we introduce the Simulator of Non- Uniform Cache Architectures (SiNUCA). This cycle-accurate microarchitecture simulator is validated in terms of performance and energy consumption by comparing it to a real processor. Our performance results were obtained executing single-threaded applications from SPEC-CPU2006 and multi-threaded applications from SPEC-OMP2001 and NASNPB benchmark suites. The energy related results were obtained by integrating SiNUCA with the Multi-core Power, Area, and Timing (McPAT) framework and the CACTI power modeling tool. When applying our mechanisms on all the cache levels, we observe on average a 36% energy reduction for DSBP, 25% energy reduction using DEWP and an average reduction of 37% in the energy consumption applying DSBP on L1 and L2 and DEWP on the LLC. All these reductions caused a negligible performance loss of less than 4% on average.

Orientador: Carlos Alberto Mariotoni / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Civil, Arquitetura e Urbanismo / Made available in DSpace on 2018-08-09T15:15:44Z (GMT). No. of bitstreams: 1 Gomazako_MarconeSusumo_D.pdf: 5293277 bytes, checksum: 54ecece1926586b33b8eb4664a564549 (MD5) Previous issue date: 2007 / Resumo: Este trabalho vem apresentar um panorama do sistema elétrico geralmente encontrado em construções comerciais de grande porte, com cerca de trinta anos de funcionamento, que operam de forma pouco eficiente para os parâmetros atuais, principalmente no seu sistema de ar condicionado central. Nessa construção (estudo), seu sistema de condicionamento ambiental representa um acréscimo na demanda energética de cerca de 60%, passando de 450.000 kWh/mês para 750.000 kWh/mês, e a troca desses equipamentos por mais modernos e eficientes, significaria grandes investimentos, tornando-se inviável no curto prazo. Com isso, elaborou-se um protótipo contendo dispositivos de automação, que podem ser incorporados ao sistema existente, sem grandes dificuldades, e minimizando os custos operacionais com o sistema. Esses dispositivos permitem um monitoramento mais eficiente, sem a necessidade desses investimentos, como a substituição de grandes equipamentos (compressores, chillers, etc.) que fazem parte do sistema de ar condicionado central. Esse protótipo permitiu demonstrar que com a aplicação desses dispositivos incorporados nesses sistemas, podem gerar uma economia de cerca de 20% no consumo de energia elétrica, que representa uma economia bastante significativa de 60.000 kWh/mês (neste caso) quando operado o sistema de ar condicionado, além de aliviar os recursos humanos disponibilizados para esse tipo de monitoramento / Abstract: This work comes to present a panorama of the electric system found usually in commercial constructions of great load, with about thirty years of operation, that operate in way a little efficient for the current parameters, mainly in her air conditioning system. In that construction (in study), her system of environmental conditioning represents an increment in the energy demand of about 60%, passing to the 450.000 kWh/month for 750.000 kWh/month, and the change of those equipments for more modern and efficient, it would mean great investments, becoming unviable in the short period. With that, a prototype was elaborated containing automation devices, that can be incorporate to the existent system, without great difficulties, and minimizing the operational costs with the system. Those devices allow a more efficient monitoring, without the need of those investments, as the substitution of great equipments (compressors, chillers, etc.) that they part of the system of air conditioned central. That prototype allowed to demonstrate that with the application of those incorporate devices in those systems, they can generate an economy of about 20% in the electric power consumption, that represents a quite significant economy of 60.000 kWh/month, (this case) when operated the system of conditioned air, besides relieving the human resources made available for that monitoring type / Doutorado / Recursos Hidricos, Energeticos e Ambientais / Mestre em Engenharia Civil

Wireless Sensor Networks (WSNs), in addition to enabling monitoring solutions for numerous new applications areas, have gained huge popularity as a cost-effective, dynamically scalable, easy to deploy and maintainable alternatives to conventional infrastructure-based monitoring solutions. A WSN consists of spatially distributed autonomous wireless sensor nodes that measure desired physical phenomena and operate in a collaborative manner to relay the acquired information wirelessly to a central location. A wireless sensor node, integrating the required resources to enable infrastructure-less distributed monitoring, is constrained by its size, cost and energy. In order to address these constraints, a typical wireless sensor node is designed based on low-power and low-cost modules that in turn provide limited communication and processing performances. Data and computation intensive wireless monitoring applications, on the other hand, not only demand higher communication bandwidth and computational performance but also require practically feasible operational lifetimes so as to reduce the maintenance cost associated with the replacement of batteries. In relation to the communication and processing requirements of such applications and the constraints associated with a typical wireless sensor node, this thesis explores energy efficient wireless sensor node architecture that enables realization of data and computation intensive applications. Architectures enabling raw data transmission and in-sensor processing with various technological alternatives are explored. The potential architectural alternatives are evaluated both analytically and quantitatively with regards to different design parameters, in particular, the performance and the energy consumption. For quantitative evaluation purposes, the experiments are conducted on vibration and image-based industrial condition monitoring applications that are not only data and computation intensive but also are of practical importance. Regarding the choice of an appropriate wireless technology in an architecture enabling raw data transmission, standard based communication technologies including infrared, mobile broadband, WiMax, LAN, Bluetooth, and ZigBee are investigated. With regards to in-sensor processing, different architectures comprising of sequential processors and FPGAs are realized to evaluate different design parameters, especially the performance and energy efficiency. Afterwards, the architectures enabling raw data transmission only and those involving in-sensor processing are evaluated so as to find an energy efficient solution. The results of this investigation show that in-sensor processing architecture, comprising of an FPGA for computation purposes, is more energy efficient when compared with other alternatives in relation to the data and computation intensive applications. Based on the results obtained and the experiences learned in the architectural evaluation study, an FPGA-based high-performance wireless sensor platform, the SENTIOF, is designed and developed. In addition to performance, the SETNIOF is designed to enable dynamic optimization of energy consumption. This includes enabling integrated modules to be completely switched-off and providing a fast configuration support to the FPGA.  In order to validate the results of the evaluation studies, and to assess the performance and energy consumption of real implementations, both the vibration and image-based industrial monitoring applications are realized using the SENTIOF. In terms of computational performance for both of these applications, the real-time processing goals are achieved. For example, in the case of vibration-based monitoring, real-time processing performance for tri-axes (horizontal, vertical and axial) vibration data are achieved for sampling rates of more than 100 kHz. With regards to energy consumption, based on the measured power consumption that also includes the power consumed during the FPGA’s configuration process, the operational lifetimes are estimated using a single cell battery (similar to an AA battery in terms of shape and size) with a typical capacity of 2600 mA. In the case of vibration-based condition monitoring, an operational lifetime of more than two years can be achieved for duty-cycle interval of 10 minutes or more. The achievable operational lifetime of image-based monitoring is more than 3 years for a duty-cycle interval of 5 minutes or more.

Master of Architecture / Department of Architecture / Gary J. Coates / Buildings account for a large part of total U.S. energy consumption and generate far more greenhouse gas emissions than any other sector of the economy. The purpose of this thesis is to demonstrate how buildings can be designed in a way that helps to mitigate global environmental problems, while resolving local urban design, architecture and social issues. This purpose was achieved by designing a zero-energy garage apartment for a site located along an alley in Manhattan, Kansas. The methodology for the design was to: identify a client; define project goals and design criteria; determine solar and geothermal renewable energy system requirements; design the garage apartment by employing energy efficient strategies relating to bioregional design and passive solar design; identify eco-friendly materials obtainable within a 500-mile radius of the site; and identify energy-efficient construction methods. The energy performance of the garage apartment was constantly monitored using eQUEST and Energy-10 simulation softwares. Operational definitions: Garage apartment- a building behind the main building[superscript]1, which is part of the same plot as the main building. It is also called a 'backhouse', 'granny flat' or a 'rear house'. Zero-energy house- for this thesis, a grid connected self-standing zero-energy house, which results in zero utility bills throughout the year.

The UK’s housing stock is among the oldest and least efficient in Europe. 85% of the UK’s existing homes will still be standing and in use in 2050. Improving the energy efficiency of UK housing stock is an essential requirement in order for the UK to meet its 2008 Climate Change Act obligations. Energy efficiency in buildings is the focus of European (EU) policies with the intention of creating a low-carbon economy by 2020. Reducing energy consumption in existing buildings is essential to achieving this. Government policies are the primary mechanism for lowering energy consumption through changing consumer behaviour, promoting low carbon technology and energy efficient renovations of old building stock.The objective of this thesis is to investigate the effectiveness of UK policies at addressing factors affecting consumer decisions to carry out energy efficient renovations. This is with the intention of determining if UK policies are effectively contributing to the government’s long term climate change commitments.Using a theory developed by Parker (2000) as a conceptual framing of policy compliance, this study conducts interviews with consumers in order to analyse their awareness, understanding and perception of UK energy efficiency policies. Therefore, it can be determined how effective policies are at affecting consumer decisions to carry out energy efficient renovations.The thesis informs that consumers are motivated and willing to comply with policies but there are several key barriers preventing them from complying with these policies and therefore adopting energy efficient renovations. Policies are deemed to be somewhat ineffective at affecting consumer decisions to carry out energy efficient renovations.

Wireless Sensor Networks (WSNs) refer to a group of spatially deployed devices which are used to monitor or detect phenomena, and have the ability to relay sensed data and signalling wirelessly. Positioning information in WSNs is absolutely crucial to perform tasks such as intelligent routing, data aggregation and data collection optimally. A need exists for localisation algorithms which are scalable, distributed, energy efficient and easy to deploy. This research proposes a beaconless Cluster-based Radial Coordinate Establishment (CRCE) positioning algorithm to locate sensor nodes relative to a local coordinate system. The system does not make use of Global Positioning System (GPS) or any other method to provide apriori position information for a set of nodes prior to the CRCE process. The objective of CRCE is to reduce energy consumption while providing a scalable coordinate establishment method for use in WSNs. To reduce energy consumption during the node positioning process, the research focuses on minimising the number of message exchanges in the network by implementing a cluster-based network topology and utilising the potential of geographically distributed processors. A radial coordinate convergence process is proposed to achieve scalability as the number of sensors in the network increases. Three other localisation algorithms are investigated and compared to CRCE to identify the one best suited for coordinate establishment in WSNs. Two of these comparison algorithms are published in the literature and the other is a modified version of one of the published algorithms. The results show a significant decrease in the number of messages that are necessary to establish a network-wide coordinate system successfully, ultimately making it more scalable and energy efficient. In addition, position based algorithms, such as location based routing, can be deployed on top of CRCE. / Dissertation (MEng (Computer Engineering))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted

O consumo de energia se torna cada vez mais importante para a arquitetura de processadores, onde o número de cores dentro de um mesmo chip está aumentando mas o total de energia disponível se mantém no mesmo nível ou até mesmo se reduz. Assim, técnicas para economizar energia, tais como opções de escala de frequência e desligamento automático de subsistemas, estão sendo usadas para manter a troca entre energia e desempenho. Para se obter alto desempenho, os atuais Chip Multiprocessors (CMPs) integram grandes memórias cache a fim de reduzir a latência média para acesso a memória principal, através da alocação do conjunto de dados da aplicação dentro do chip. Essas memórias cache tem sido projetadas tradicionalmente para explorar a localidade temporal usando políticas de substituição inteligentes e localidade espacial buscando todos os dados da linha da cache após uma falta de dados. Entretanto, estudos recentes mostraram que o número de sub-blocos dentro da linha da memória cache, que são realmente usados, costuma ser baixo, sendo que, os sub-blocos que são usados recebem poucos acessos antes de se tornarem mortos (isto é, nunca mais são acessados). Além disso, muitas da linhas da memória cache permanecem ligadas por longos períodos de tempo, mesmo que os dados não sejam usados novamente ou são inválidos. Para linhas de cache modificadas, a memória cache aguarda até que a linha seja expulsa para que esta seja gravada (write-back) de volta no próximo nível de memória. Essas escritas competem com as requisições de leitura (demanda do processador e prébusca da cache), aumentando a pressão no controlador de memória. Por essas razões, a eficiência energética e o desempenho das memórias cache não são ideais. Essa tese propõe a aplicação de preditores de uso de linhas da cache para aumentar a eficiência energética das memórias cache. São propostos os mecanismos Dead Sub-Block Predictor (DSBP) e Dead Line and Early Write-Back Predictor (DEWP) para permitir economia de energia sem que haja degradação do desempenho. DSBP é usado para prever quais sub-blocos da linha da cache serão usados e quantas vezes eles serão acessados de forma a trazer para a cache apenas os sub-blocos úteis e desliga-los após eles serem acessados pelo número de vezes previsto. DEWP prevê linhas de cache mortas assim que elas recebem o último acesso, desligando essas linhas. As linhas sujas são escalonadas para sofrerem write-back após a última operação de escrita, aumentando o potencial de salvar energia, reduzindo também a pressão no controlador de memória. Ambos os mecanismos propostos também reduzem a poluição nas memórias cache, dando prioridade para a expulsão de linhas mortas, melhorando as atuais políticas de substituição. Embora cada mecanismo apresentado seja capaz de funcionar separadamente dentro do sistema, ambos os mecanismos podem também ser misturados em uma mesma hierarquia de cache. Essa implementação mista é interessante pois a granularidade de sub-bloco é preferível para níveis de cache próximos do processador, onde as linhas de memória cache são expulsas rapidamente, enquanto o último nível de cache tende a usar toda a linha antes da sua expulsão. Com o intuito de avaliar os mecanismos propostos, é apresentado o Simulator of Non- Uniform Cache Architectures (SiNUCA). Esse simulador de microarquitetura com precisão de ciclos é validado em termos de desempenho e consumo de energia através da comparação com um processador real. Os resultados de desempenho foram obtidos executando aplicações das cargas de trabalho single-threaded do conjunto SPEC-CPU2006 e aplicações multi-threaded dos conjuntos SPEC-OMP2001 e NAS-NPB. Os resultados relativos a energia foram obtidos integrando o SiNUCA com as ferramentas de modelagem Multi-core Power, Area, and Timing (McPAT) e CACTI. Quando aplicados os mecanismos em todos os níveis de memória cache, observou-se em média uma redução de 36% no consumo de energia usando o DSBP, 25% usando o DEWP e 37% quando usou-se o DSBP nos níveis L1 e L2 e o DEWP no último nível. Todas essas reduções causaram uma perda desprezível de desempenho de menos de 4% em média. / Energy consumption is becoming more important for processor architectures, where the number of cores inside the chip is increasing and the total power budget is kept at the same level or even reduced. Thus, energy saving techniques such as frequency scaling options and automatic shutdown of sub-systems are being used to maintain the trade-off between power and performance. To deliver high performance, current Chip Multiprocessors (CMPs) integrate large caches in order to reduce the average memory access latency by allocating the applications’ working set on-chip. These cache memories have traditionally been designed to exploit temporal locality by using smart replacement policies, and spatial locality by fetching entire cache lines from memory on a cache miss. However, recent studies have shown that the number of sub-blocks within a line that are actually used is often low, and those sub-blocks that are used are accessed only a few times before becoming dead (that is, never accessed again). Additionally, many of the cache lines remain powered for a long period of time even if the data is not used again, or is invalid. For modified cache lines, the cache memory waits until the line is evicted to perform the write-back to next memory level. These write-backs compete with read requests (processor demand and cache prefetch), increasing the pressure on the memory controller. For these reasons, the energy efficiency and performance of cache memories are not ideal. This thesis introduces cache line usage predictors to increase the energy efficiency of cache memories. We propose the Dead Sub-Block Predictor (DSBP) and Dead Line and Early Write-Back Predictor (DEWP) mechanisms to enable energy savings without performance degradation. DSBP is used to predict which sub-blocks of a cache line will be actually accessed and how many times they will be used in order to bring into the cache only those sub-blocks that are necessary, and power them off after they are accessed the predicted number of times. DEWP predicts dead lines as soon as they receive the last access, and turns off these lines. Dirty lines are scheduled for write-back after the last write operation occurs, increasing the energy savings potential and also reducing the pressure on the memory controller. Both proposed mechanisms also reduce pollution in cache memories by prioritizing dead lines for eviction in the existing replacement policy. Although each introduced mechanism is capable of performing separately inside a system, both mechanisms can also be mixed in the same cache hierarchy. This mixed implementation is interesting because the sub-block granularity is more suitable for cache levels closer to the processor, where the cache lines are quickly evicted, while the Last- Level Cache (LLC) tends to use the whole cache line before its eviction. In order to evaluate our proposed mechanisms, we introduce the Simulator of Non- Uniform Cache Architectures (SiNUCA). This cycle-accurate microarchitecture simulator is validated in terms of performance and energy consumption by comparing it to a real processor. Our performance results were obtained executing single-threaded applications from SPEC-CPU2006 and multi-threaded applications from SPEC-OMP2001 and NASNPB benchmark suites. The energy related results were obtained by integrating SiNUCA with the Multi-core Power, Area, and Timing (McPAT) framework and the CACTI power modeling tool. When applying our mechanisms on all the cache levels, we observe on average a 36% energy reduction for DSBP, 25% energy reduction using DEWP and an average reduction of 37% in the energy consumption applying DSBP on L1 and L2 and DEWP on the LLC. All these reductions caused a negligible performance loss of less than 4% on average.

Syftet med det här examenarbetet har varit att analysera ett flerbostadshus som redan har energieffektiviserats med vanliga energieffektiviseringsåtgärder för att ytterligare installera andra energiåtgärder som är lönsamma och kan minska den inköpta energin.Bygg- och fastighetssektorns står för ungefär 40% av energianvändningen i Sverige. En stor del av denna energianvändning går det att minska genom att utföra energieffektiviseringsåtgärder på befintliga byggnader. Sverige har ett miljömål som är att nå ett nettoutsläpp år 2045 och bostadssektorn har en stor potential för att underlätta att Sverige når sitt energimål. Vanliga energieffektiviseringsåtgärder i flerbostadshus är bland annat fasad- och vindisolering, fönsterbyte och att installera mer energieffektiva ventilationssystem och belysningar. Exempelhuset har redan fått vindisolering, fasadputsning, treglasfönster, energieffektiva LED-lampor och en ny undercentral. Detta har resulterat i en specifik energianvändning som låg på ca 108 kWh/m2 år 2020. I Sverige ligger den genomsnittliga specifika energianvändningen på flerbostadshus ca 134 kWh/m2. För att få ner den specifika energianvändningen ännu mer har fyra andra energieffektiviseringsåtgärder undersökts och analyserats med avseende på sina energibesparingspotentialer och lönsamheter. De valda åtgärderna är en solvärmeanläggning, en solcellanläggning, snålspolande armaturer och en spillvattenvärmeväxlare (Ekoflow). Den specifika energianvändningen har gått ner till 90 kWh/m2 efter dessa energibesparingsåtgärder har utförts. Det visade sig att de snålspolande armaturerna, solcellanläggningen och solvärmeanläggningen är lönsamma. Däremot visade resultatet att spillvärmeväxlaren (Ekoflow) inte är lönsam. Men genom att paketera alla åtgärder har det lyckats att uppfylla lönsamhetskravet och att få en gemensam internränta som är högre än kalkylräntan. Kalkylräntan antas vara 5 % och internräntan har beräknats 6,45 %.Lönsamheten är förstås beroende på framtida energipriser såsom fjärrvärme-och elpriser. På energimarknaden kostar en kWh el ca 1,82 kr och en kWh värme ca 0,847 kr för konsumenter. Med hjälp av annuitetskalkyl har kostnaden för en kWh som alstras genom solvärmeanläggning och solcellanläggningen beräknats. För solvärme kostar 0,75 kr/kWh och för solel kostar 1 kr/kWh. Detta är fast pris under 30 år, alltså under kalkyltiden och denna energi är billigare jämfört med energin på marknaden. / The purpose of this thesis was to analyse an apartment building that has already been implemented with standard energy efficiency measures to further install other energy efficiency measures that are profitable and can reduce the purchased energy.The building sector is responsible for about 40 percent of energy use in Sweden. A large part of this energy use can be reduced by installing energy efficiency measures on existing buildings. Sweden has an environmental goal which is to reach a net emission by 2045 and the building sector has great potential to facilitate for Sweden to reach its energy goal.Common energy efficiency measures for multi-family buildings include insulation of external walls and attic insulation, window replacement, installing more energy-efficient ventilation systems and upgrading the lighting system. The example house has already received an attic insulation, facade plastering, triple-glazed windows, energy-efficient LED lamps and a district heating substation. This has resulted in a specific energy use that was 108 kWh / m2 in 2020 and in Sweden the average specific energy use is 134 kWh / m2 in apartment buildings.To reduce more the specific energy use, 4 energy efficiency measures have been investigated to be able to assess their potential of energy use reduction and profitability. These measures are a solar heating system, a photovoltaic system, Energy-efficient taps, and a wastewater heat exchanger (Ekoflow). The specific energy consumption has decreased to 90 kWh / m2 after these energy saving measures have been implemented. It turned out that the Energy-efficient taps, the photovoltaic system, and the solar heating system are profitable and Ekoflow is not profitable. But by collecting all measures in a package, it has been succeeded to fulfil the profitability requirement and to obtain a common internal rate of return which is higher than the discount rate. The discount rate is assumed to be 5% and the internal rate of return has been calculated at 6.45%.Profitability is dependent on future energy prices such as district heating and electricity prices. The market price is one kWh of electricity about 1.82 SEK and one kWh of heat costs about 0.847 SEK. Using an annuity calculation, the cost for a kWh obtained through a solar heating system and the solar cell system has been calculated. For the solar collector is calculated 0.75 SEK / kWh, and for the photo voltaic become 1 SEK / kWh. It will be a fixed price during the calculation period which is 30 years, and that means that this energy is cheaper than the energy on the market.

This thesis deals with a design of an energy-efficient hotel in the Jeseníky mountains. Main parts of the project are to be found in folder C, containing the drawings including five technical details, technical report with attached list of compounds, thermal assessment and fire safety project. The work also contains a study in folder B, which represents the initial version of the project, including the evolution of the project, staircase calculation and simple visualization. This thesis can be used as project documentation for actual building operation.

In relation to energy savings, the development of constructing energy-saving houses, which includes low-energy, passive and zero houses, started to be created. The diploma thesis helps readers to be better informed about energy-saving houses, their development during history and their main features. The last two chapters show the development of constructing energy-saving houses in the Czech Republic in graphs. They also show in which regions are these houses built the most and which construction system and way of using is preferred.