Techn. University, Diss., 2004--Berlin.

Η παρούσα εργασία αποσκοπεί στη μελέτη του προβλήματος του χρονοπρογραμματισμού γεγονότων, την τοποθέτηση δηλαδή των γεγονότων σε υποδοχείς χρόνου και χώρου, με τη χρήση Γενετικών Αλγορίθμων. Μελετήσαμε τo πρόβλημα του χρονοπρογραμματισμού στην Εκπαίδευση και ειδικότερα σε ένα Πανεπιστήμιο, που εμφανίζεται σε δύο εκδοχές: το πρόβλημα χρονοπρογραμματισμού εξετάσεων και το πρόβλημα χρονοπρογραμματισμού διαλέξεων, καθώς και τα αντίστοιχα πειράματα και τα αποτελέσματα αυτών. Χρησιμοποιώντας το λογισμικό FET που βασίζεται στους Γενετικούς Αλγόριθμους κατασκευάσαμε χρονοδιαγράμματα για το ωρολόγιο πρόγραμμα του Μεταπτυχιακού Προγράμματος του Διατμηματικού του Πανεπιστημίου Πατρών "Μαθηματικά των Υπολογιστών και των Αποφάσεων" των τμημάτων Μαθηματικών και Μηχανικών Η/Υ και Πληροφορικής και παρουσιάσαμε τα αποτελέσματα αυτών. / The aim of this paper is the study of the timetabling problem, meaning the allocation of events in time-slots and space-slots, using Genetic Algorithms. We studied the Education Timetabling problem for a University which appears in two versions, timetabling of exams and timetabling of lectures and its corresponding experiments and results. Using the open source free software FET which is based on the Genetic Algorithms, we scheduled timetables for the weekly program of Postgraduate Program of University of Patras "Mathematics of Computers and Decision" in which participate two departments, the department of Mathematics and the department of Engineering Computing and Information Technology and we presented the results of those.

A variety of genes that influence aging have been identified in a broad selection of organisms including Saccharomyces cerevisiae (yeast), Caenorhabditis elegans (worms), Drosophila (fruit flies), Macaca Mulatta (rhesus monkeys), and even Homo sapiens. Many of these genes, such the TOR’s, FOXO’s, AKT’s, and S6K’s are conserved across different organisms. All of these genes participate in nutrient sensing networks. Other conserved genetic networks may similarly affect lifespan. In this thesis, I explored genes from an iron metabolism family and a heat shock protein (HSP) gene family that have been identified, but not confirmed, to influence lifespan. Yeast is a reliable model for mitotic (replicative) aging. Using yeast, I tested whether the FET-genes, encoding a family of iron importer-related genes, are required for mitotic lifespan. I also tested whether another family of genes, the yeast SSA HSP70- encoding genes, related to mammalian HSP70s, influence mitotic aging. I primarily used the replicative lifespan (RLS) assay, in which I measured the mitotic capacity of multiple FET and SSA yeast mutants. I hypothesize that aging occurs when iron transport is misregulated, which may lead to an over-reliance on HSPs for lifespan maintenance. The results presented in this thesis support the hypothesis. First, FET3 was primarily involved in lifespan maintenance under normal conditions (2% glucose), while FET5 was primarily involved in the cellular lifespan extension characteristic of caloric restriction (0.01% glucose), a known anti-aging intervention. In addition, SSA2 appeared to facilitate lifespan maintenance in the absence of FET4, while the presence of SSA1 limited lifespan length. That the aging genes identified in this study are involved in iron metabolism or heat stress suggests that protein aggregation or reactive oxidative species production are common processes through which these genes interact.

abstract: To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor performance but the stress is non-uniformly distributed in the channel, leading to systematic performance variations. In this dissertation, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. On the other hand, semiconductor devices with self-feedback mechanisms are emerging as promising alternatives to CMOS. Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstances, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. A new threshold voltage model for Fe-FET is developed, and is further revealed that the impact of random dopant fluctuation (RDF) can be suppressed. Furthermore, through silicon via (TSV), a key technology that enables the 3D integration of chips, is studied. TSV structure is usually a cylindrical metal-oxide-semiconductors (MOS) capacitor. A piecewise capacitance model is proposed for 3D interconnect simulation. Due to the mismatch in coefficients of thermal expansion (CTE) among materials, thermal stress is observed in TSV process and impacts neighboring devices. The stress impact is investigated to support the interaction between silicon process and IC design at the early stage. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

Magister Educationis - Med / According to Morrison (2007), bullying is considered a critical issue in the Western Cape Schools as well as in South African schools in general. This phenomenon of bullying can affect learners in schools and may lead to several problems such as low esteem, poor academic performance, depression, absenteeism and eventually dropping out of school. In addition, numerous studies in psychology have revealed that physical activity has positive effects on learners, (Ajay, 2011; Shaffer, 2002). This is because it increases self-esteem in learners, boosts confidence and builds the physical, social, emotional, moral and intellectual composition in an individual. This study will aim (1) to determine the relationship between bullying and physical activity among South African learners in one high school in the Western Cape, (2) to measure the frequency of bullying at that high school, (3) to measure the frequency of bully-victimization in the school among South African learners in that high school in the Western Cape, and (4) to establish the level of physical activity by the learners in the high school. This study used a quantitative method and a descriptive survey as research design. The participants were mostly black South African adolescent learners, aged between 14 and 20 years.

Magister Commercii (Infomation Management) / The aim of this research was to investigate the use of social media (SM) in improving the quantity and quality of passes in computer programming in South Africa’s Further Education and Training (FET) colleges. The study addresses the high learner failure rates in computer programming at National Certificate (Vocational) (NCV) level 3. A preliminary investigation identified that increased lecturer contact time with the students could positively affect the quantity and quality of passes in computer programming. The social medium of Facebook (FB) was studied to assess whether it could enhance contact time with students. In investigating factors affecting computer programming passes at the College of Cape Town, the study identified how SM technologies can assist in increasing contact time for students outside normal college time. Four groups on FB were created to allow learners to ask questions, interact with the lecturer and peers on the subject. A mixed approach was employed using qualitative and quantitative data. Test scores for previous years (2011) were compared to current (2012) test scores for the NCV 3 learners. Statistical functions calculated the average passes and total number of passes. Furthermore, a total of thirty questionnaires were used to check the learners’ perceptions toward the use of SM outside the class to enhance performance.. More lecturer contact time on FB for one student group scored better in terms of the quantity and quality of passes. The groups using FB (with more practice time or more technical contact time) produced results which were far better than in previous years (2010 and 2011). The fourth group using FB for more peer interaction also did fairly well with an increase at the end of the year (2012) of 35% pass in programming at level 3 - up from 30% in 2011. It is the researcher’s view that, once internet access is evenly spread, it has the potential to increase performance in subjects like computer programming. A further look at the certification of level 4 learners for programming subjects indicated an improvement could be possible by the introduction of SM at level 3 - where much of the bottleneck lies. As this research was limited to a single FET college it cannot be generalised. Further research spread across various FET colleges countrywide will serve to confirm these findings and determine new insights into the whole process of using SM to improve passes in computer programming at NCV level 3.. The practical recommendation is that FB should be used for this stated purpose. In respect of academic recommendations, the researcher intends to implement the same study with learners at level two and level four.

As more data is gathered, analysed and stored, private companies create new products and unlock new commercial frontiers. Simultaneously, governments are beginning to realise that the laws in place require a revamp for the good of commercial innovation and for execution of governmental prerogatives. Hence, in a bid to catch up with the data economy, governments have begun looking for new legal measures that allow them to legally access the data that is held by private companies. Amongst the existing solutions and sprouting suggestions, mandatory business-to-government data sharing often features as a measure through which obligations may be imposed upon private data holding companies to share their data with governments. Other governments have already put in place laws and adopted practices that impose mandatory business-to-government data sharing obligations on private companies.  Many of the countries where private enterprises carry out their businesses have entered into International Investment Agreements (IIAs) which invariably entitle investors to Fair and Equitable treatment and prohibit unlawful compensation. Against this background, this thesis discusses the subject of mandatory business-to-government data sharing by dwelling on three main issues, that is, (i) whether data is/are protected as investment, (2) whether mandatory business-to-government data sharing obligations may infringe the Fair and Equitable Treatment standard and (3) whether mandatory business-to-government data sharing obligations may amount to unlawful expropriation.

Tato diplomová práce se zabývá dotováním grafenu nízkoenergiovými elektrony. Na křemíkový substrát pokrytý vrstvou SiO2 jsou pomocí litograficky vyrobené masky nadeponované kovové kontakty z titanu a zlata. Grafen vyrobený pomocí metody depozice z plynné fáze je přenesen na substrát a slouží jako vodivé spojení kovových elektrod, které vytvářejí kolektor a emitor. Na křemík je ze spodu přivedeno napětí, které tak vytváří spodní hradlo. Takto vytvořený grafenový tranzistor je ozařován nízkoenergiovými elektrony, které mění dotování grafenu. Z polohy maxima v závislosti odporu grafenu na hradlovém napětí lze vyčíst typ dotování. Toto maximum udává napětí, při kterém Fermiho meze grafenu prochází Diracovým bodem v pásové struktuře grafenu. Velikost hradlového napětí, primární energie elektronového svazku a proud svazku jsou tři parametry, které mají velký vliv na změny dotování. Při ozařování transistoru dochází ke změně typu dotování právě tehdy, když odpor grafenu v závislosti na hradlovém napětí dosáhne maxima. Vývoj této změny je zkoumán pro různé energie a proudy primárního svazku v závislosti na hradlovém napětí i v čase. Typ dotování je také prozkoumán při zastavení ozařování v různých fázích smyčky hradlového napětí. Dopování grafenu nízkoenergiovými elektrony je popsáno v teoretickém modelu.

This diploma thesis is focused on fabrication of graphene field-effect transistors, characterisation of their transport properties and investigation of low-energy electron beam influence on the devices' properties under UHV conditions. The theoretical part of this work describes graphene fabrication methods, options of graphene transfer onto the substrates for graphene field-effect transistor manufacture. Furthermore, model of graphene doping via electrostatic interaction or photon, resp. electron beam exposition is explained. The experimental part of this work consist of manufacture of the graphene field-effect transistor in order to examine the change of its transport properties induced by doping of the graphene via low-energy electron beam exposition.

This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.