ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Orthogonal frequency division multiplexing (OFDM) is a new technique for data transmission. Conforming to the final draft of OFDM-based DVB-T (ETSI EN 300 744 V1.6.1), which is intended for digital terrestrial television broadcasting, a DVB-T baseband system is designed. The system performance is simulated in MATLAB using Simulink. Then it is implemented on Field Programmable Gate Array (FPGA) with the help of System Generator software. The result shows that OFDM is robust against multipath effect and convenient for implementation as well, thus owning a quite promising future.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.

Since its introduction in the 1980s, field-programmable gate arrays have seen a growing use over the years. Nowadays FPGAs are found in everything from planetary rovers and base transceiver stations to bitcoin miners. With the technological advancements and the growth of the market, there has been a steady flow of new models with increasing capacity. To make it possible to use this capacity in an efficient way, also the software tools have been improved. The applications in research have grown and so has the will to compare both the speed and size between different implementations that try to solve the same or similar problem. However, how to make a good comparison is not well defined. Since few research papers have source code available, such comparisons are hard to make and there is a high risk of comparing apples to pears. In this thesis, we will study the impact of different software settings and design constraints on the FPGA design flows to better understand how to report research results. This will be done by running selected designs through different EDA tools, using various settings and finally analyse the data the tools provide. At the end we will begin to define guidelines for how to report and compare implementation data, to give a good account of their performance compared to other designs.

This thesis presents the results of an architectural study on the design of FPGA- based architectures for convolutional neural networks (CNNs). We have analyzed the memory access patterns of a Convolutional Neural Network (one of the biggest networks in the family of deep learning algorithms) by creating a trace of a well-known CNN architecture and by developing a trace-driven DRAM simulator. The simulator uses the traces to analyze the effect that different storage patterns and dissonance in speed between memory and processing element, can have on the CNN system. This insight is then used create an initial design for a layer architecture for the CNN using an FPGA platform. The FPGA is designed to have multiple parallel-executing units. We design a data layout for the on-chip memory of an FPGA such that we can increase parallelism in the design. As the number of these parallel units (and hence parallelism) depends on the memory layout of input and output, particularly if parallel read and write accesses can be scheduled or not. The on-chip memory layout minimizes access contention during the operation of parallel units. The result is an SoC (System on Chip) that acts as an accelerator and can have more number of parallel units than previous work. The improvement in design was also observed by comparing post synthesis loop latency tables between our design and one with a single unit design. This initial design can help in designing FPGAs targeted for deep learning algorithms that can compete with GPUs in terms of performance.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper describes the design of a PC plug-in card that incorporates all functions of the base band segment of a PCM decommutator which includes the bit synchroniser (BS), frame synchroniser (FS) and subframe synchroniser (SFS). FPGAs are used for the realization of the digital sections of the circuit. The card is capable of handling all standard IRIG codes. The bit synchroniser can handle data rates upto 1Mbps (NRZL), while the frame and subframe synchronisers have been designed to work upto 10 Mbps.

Les travaux de recherche présentés se situent dans le contexte des méthodologies d’aide à l’implémentation d’algorithmes graphe flot de données sur architectures reconfigurables dynamiquement de type RSoC (Reconfigurable System on Chip) à base de technologie FPGA. La stratégie visée consiste à mettre en œuvre une approche de conception basée simultanément sur la reconfiguration dynamique (RD) et la synthèse architecturale (SA) en vue d’atteindre la meilleur Adéquation Algorithme Architecture (A3). La méthodologie consiste à identifier et extraire les parties d’une application décrite sous forme d’un GFD afin de les implanter soit par partie successivement reconfigurées (PT), soit par la SA ou bien en combinant les deux méthodes. Pour développer notre solution dans un but d’optimisation et de juste compromis entre les deux approches RD et SA, nous avons défini un paramètre permettant une évaluation du degré inter-partition de mise en œuvre d’unités fonctionnelles partagées. Afin de valider la stratégie méthodologique proposée, nous présentons les résultats de l’application de notre approche sur deux applications temps réel. Une analyse comparative en terme de résultats d’implémentation illustre l’intérêt et la capacité d’optimisation de cette méthode pour l’implémentation en reconfiguration dynamique d’applications complexes sur RSoC. / AThe research work presented in the context of methodologies is to assist the implementation of data flow graph algorithms on dynamically reconfigurable RSoC (Reconfigurable System on Chip)-based FPGA architectures.The main strategy consists in implementing a design approach based on simultaneously both the dynamic reconfiguration (DR) and synthesis architecture (SA) in order to achieve a best Adequacy Algorithm Architecture (A3). The methodology consists in identifying and extracting the parts of an application which is described in form of DFG in order to implement either by successively partial reconfiguration (TP), or by the AS or by combining the two approaches.To develop our solution with a view of optimizing and suitable compromise between the two approaches RD and SA, we propose a parameter in order to evaluate the degree of the inter-partition implementation based on functional units shared. In order to validate the proposed methodological strategy, we present the results of the implementation of our approach on two real-time applications. A comparative analysis with the respecting of the implementation results illustrates the interest and the optimisation ability of our method, which is also for dynamic reconfiguration implementation of the complex applications on RSoC.

The Field Programmable Gate Array (FPGA) has been used for decades in embedded applications where custom hardware is not practical or feasible. However, thanks to increases in size and compute capabilities, the FPGA has become more attractive as an option to supplement a general-purpose Central Processing Unit (CPU) for accelerating complex computations used for encryption, machine learning, and many other applications. Although FPGAs have already appeared in embedded Systems-on-Chip (SoC) and cloud environments, the reconfigurable nature of FPGAs creates security vulnerabilities not found in more traditional accelerators like Graphics Processing Units (GPU). In this paper, we describe a vulnerability in an Altera Cyclone V SoC and demonstrate an attack that exploits this vulnerability. We propose a hardware modification that would provide a defense against this attack, and we implement a Linux kernel module to demonstrate a proof-of-concept for this hardware solution.

Current FPGAs can implement large systems because of the high density of reconfigurable logic resources in a single chip. FPGAs are comprehensive devices that combine flexibility and high performance in the same platform compared to other platform such as General-Purpose Processors (GPPs) and Application Specific Integrated Circuits (ASICs). The flexibility of modern FPGAs is further enhanced by introducing Dynamic Partial Reconfiguration (DPR) feature, which allows for changing the functionality of part of the system while other parts are functioning. FPGAs became an important platform for digital image processing applications because of the aforementioned features. They can fulfil the need of efficient and flexible platforms that execute imaging tasks efficiently as well as the reliably with low power, high performance and high flexibility. The use of FPGAs as accelerators for image processing outperforms most of the current solutions. Current FPGA solutions can to load part of the imaging application that needs high computational power on dedicated reconfigurable hardware accelerators while other parts are working on the traditional solution to increase the system performance. Moreover, the use of the DPR feature enhances the flexibility of image processing further by swapping accelerators in and out at run-time. The use of fault mitigation techniques in FPGAs enables imaging applications to operate in harsh environments following the fact that FPGAs are sensitive to radiation and extreme conditions. The aim of this thesis is to present a platform for efficient implementations of imaging tasks. The research uses FPGAs as the key component of this platform and uses the concept of DPR to increase the performance, flexibility, to reduce the power dissipation and to expand the cycle of possible imaging applications. In this context, it proposes the use of FPGAs to accelerate the Image Processing Pipeline (IPP) stages, the core part of most imaging devices. The thesis has a number of novel concepts. The first novel concept is the use of FPGA hardware environment and DPR feature to increase the parallelism and achieve high flexibility. The concept also increases the performance and reduces the power consumption and area utilisation. Based on this concept, the following implementations are presented in this thesis: An implementation of Adams Hamilton Demosaicing algorithm for camera colour interpolation, which exploits the FPGA parallelism to outperform other equivalents. In addition, an implementation of Automatic White Balance (AWB), another IPP stage that employs DPR feature to prove the mentioned novelty aspects. Another novel concept in this thesis is presented in chapter 6, which uses DPR feature to develop a novel flexible imaging system that requires less logic and can be implemented in small FPGAs. The system can be employed as a template for any imaging application with no limitation. Moreover, discussed in this thesis is a novel reliable version of the imaging system that adopts novel techniques including scrubbing, Built-In Self Test (BIST), and Triple Modular Redundancy (TMR) to detect and correct errors using the Internal Configuration Access Port (ICAP) primitive. These techniques exploit the datapath-based nature of the implemented imaging system to improve the system's overall reliability. The thesis presents a proposal for integrating the imaging system with the Robust Reliable Reconfigurable Real-Time Heterogeneous Operating System (R4THOS) to get the best out of the system. The proposal shows the suitability of the proposed DPR imaging system to be used as part of the core system of autonomous cars because of its unbounded flexibility. These novel works are presented in a number of publications as shown in section 1.3 later in this thesis.

Video/Image processing is a fundamental issue in computer science. It is widely used for a broad range of applications, such as weather prediction, computerized tomography (CT), artificial intelligence (AI), and etc. Video-based advanced driver assistance system (ADAS) attracts great attention in recent years, which aims at helping drivers to become more concentrated when driving and giving proper warnings if any danger is insight. Typical ADAS includes lane departure warning, traffic sign detection, pedestrian detection, and etc. Both basic and advanced video/image processing technologies are deployed in video-based driver assistance system. The key requirements of driver assistance system are rapid processing time and low power consumption. We consider Field Programmable Gate Array (FPGA) as the most appropriate embedded platform for ADAS. Owing to the parallel architecture, an FPGA is able to perform high-speed video processing such that it could issue warnings timely and provide drivers longer time to response. Besides, the cost and power consumption of modern FPGAs, particular small size FPGAs, are considerably efficient. Compared to the CPU implementation, the FPGA video/image processing achieves about tens of times speedup for video-based driver assistance system and other applications.

"Security issues will play an important role in the majority of communication and computer networks of the future. As the Internet becomes more and more accessible to the public, security measures will have to be strengthened. Elliptic curve cryptosystems allow for shorter operand lengths than other public-key schemes based on the discrete logarithm in finite fields and the integer factorisation problem and are thus attractive for many applications. This thesis describes an implementation of a crypto engine based on elliptic curves. The underlying algebraic structure are composite Galois fields GF((2n)m) in a standard base representation. As a major new feature, the system is developed for a reconfigurable platform based on Field Programmable Gate Arrays (FPGAs). FPGAs combine the flexibility of software solutions with the security of traditional hardware implementations. In particular, it is possible to easily change all algorithm parameters such as curve coefficients, field order, or field representation. The thesis deals with the design and implementation of elliptic curve point multiplication architectures. The architectures are described in VHDL and mapped to Xilinx FPGA devices. Architectures over Galois fields of different order and representation were implemented and compared. Area and timing measurements are provided for all architectures. It is shown that a full point multiplication on elliptic curves or real-world size can be implemented on commercially available FPGAs."