Mathematical and statistical modeling of biological systems is a desired goal for many years. Many biochemical models are often evaluated using a deterministic approach, which uses differential equations to describe the chemical interactions. However, such an approach is inaccurate for small species populations as it neglects the discrete representation of population values, presents the possibility of negative populations, and does not represent the stochastic nature of biochemical systems. The Stochastic Simulation Algorithm (SSA) developed by Gillespie is able to properly account for these inherent noise fluctuations. Due to the stochastic nature of the Monte Carlo simulations, large numbers of simulations must be run in order to get accurate statistics for the species populations and reactions. However, the algorithm tends to be computationally heavy and leads to long simulation runtimes for large systems. Therefore, this thesis explores implementing the SSA on a Field Programmable Gate Array (FPGA) to improve performance. Employing the Field programmable Gate Arrays exploits the parallelism present in the SSA, providing speedup over the software implementations that execute sequentially. In contrast to prior work that requires re-construction and re-synthesis of the design to simulate a new biochemical system, this work explores the use of reconfigurable hardware in implementing a generic biochemical simulator.

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In nanotechnology, Carbon Nanotubes systems are studied with Molecular Dynamics Simulation software programs investigating the properties of molecular structure. Computational loads are very complex in these kinds of software programs. Especially in three body simulations, it takes a couple of weeks for small number of atoms. Researchers use supercomputers to study more complex systems. In recent years, by the development of sophisticated Field Programmable Gate Array (FPGA) Technology, researchers design special purpose co-processor to accelerate their simulations. Ongoing researches show that using application specific digital circuits will have better performance with respect to an ordinary computer. In this thesis, a new special co-processor, called TERSOFF2, is designed and implemented. Resulting design is a low cost, low power and high performance computing solution. It can solve same computation problem 1000 times faster. Moreover, an optimized digital mathematical elementary functions library is designed and implemented through thesis study. All of the work about digital circuits and architecture of co-processor will be given in the related chapter. Performance achievements will be at the end of thesis.

In nanotechnology, Carbon Nanotubes systems are studied with Molecular Dynamics Simulation software programs investigating the properties of molecular structure. Computational loads are very complex in these kinds of software programs. Especially in three body simulations, it takes a couple of weeks for small number of atoms. Researchers use supercomputers to study more complex systems. In recent years, by the development of sophisticated Field Programmable Gate Array (FPGA) Technology, researchers design special purpose co-processor to accelerate their simulations. Ongoing researches show that using application specific digital circuits will have better performance with respect to an ordinary computer. In this thesis, a new special co-processor, called TERSOFF2, is designed and implemented. Resulting design is a low cost, low power and high performance computing solution. It can solve same computation problem 1000 times faster. Moreover, an optimized digital mathematical elementary functions library is designed and implemented through thesis study. All of the work about digital circuits and architecture of co-processor will be given in the related chapter. Performance achievements will be at the end of thesis.

In recent years, a number of power control concepts have been studied and implementedeither in simulation or in practice for different communication systems. It is still the case that a great deal of research is being conducted within the area of energyefficient power control mechanisms for future wireless communication networksystems. However, only a limited amount of practical work has been implemented onreal test beds environment. The main goal of this thesis is to propose and develop newprototype Transmit Power Control Mechanisms (TPCM) on WARP (Wireless Open-Access Research Platform) boards for point-to-point communications, which are to bedeveloped and tested in an indoor environment. This work mainly focuses on the automaticpower control nodes, transmission and reception over-the-air. In this thesis, wehave designed and developed TPCM to adjust the power levels on a transmitter nodeby following the feedback (ACK) approach. In this case, the destination (receiver)node always sends the feedback (ACK) to transmitter node during every successfultransmission of message signal and the main focus is on a reduction in the packetloss rate (PLR), an increase in the packet reception rate (PRR) and the capacity ofthe nodes. In this real work, we have developed and measured the results based ontwo functions namely, with and without packet window function power control mechanisms. According to the measurements section, both with and without function powercontrol mechanisms proved to have better performances for different tunable parameters.If both functions are compared, then the with window function power controlmechanism was shown to produce better performances than the without windowpower control mechanism and it also converged faster than the without window function.If consideration was given to controlling a reduction in packet loss rate, thenthe with widnow function offered higher performances than those without the windowfunction. In this regard, it was found that the with window function has acheived amaximum packet reception rate than that for the without window function for differenttunable parameters. In relation to the power consumption scenario, it was determinedthat the without window fuction proved to produce energy saving performances thanthe with window function. There are several interesting aspects of the transmit powercontrol mechanisms highlighted in the results and discussion chapter.

We present Roko, a system that allows parallelization of sequential C codes with a modest user intervention. The user exposes parallelism at the function level by annotating the code with pragmas. Roko defines only two pragmas: the parallel pragma is used to denote function calls that will be executed asynchronously, and the exposed pragma is used to describe data usage of the marked function calls. Architecturally, Roko consists of three components: a compiler that analyzes pragmas, a software environment that spreads the execution over multiple processors, and a hardware support that implements a novel synchronization scheme, versioning. We have designed, implemented and evaluated an FPGA-based prototype of Roko. Our experimental evaluation shows: (i) that few simple pragmas are all that is needed to expose parallelism in benchmark applications and (ii) that Roko can deliver good performance in terms of application speedup.

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework where user-designated software functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor. To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the performance of accelerators. An extensive range of cache architectures are explored, and results show that certain cache architectures significantly outperform others in a processor/accelerator system.

At Saab Aerospace in Linköping, components for measurement systems to the fighter aircraft JAS 39 Gripen are developed. In this activity you sometimes want to record the traffic transmitted on the data busses that connects different sys-tems. This traffic on the data busses is using the military standard MIL-STD-1553. This project has aimed to create a system for recording and sending 1553-data. The system is used on an ordinary personal computer, equipped with a recon- figurable I/O card that among others has a programmable logic circuit (FPGA). The recorded data are stored on a hard drive. The system has a graphical user interface, where the user can configure different methods of filtering the data, and other preferences. The completed system has currently the capacity to record one channel. This works excellent and the system basically meets all the requirements stated at the start of the project. By using this system instead of the commercial available systems on the market one will get a competitive alternative. If the system where to be developed further, with more channels, it would get even more price worth. Both in case of price per channel, but also in functionality. This is because it is possible to design exactly the functions the user demands. But the current version is already fully functional and competitive compared to commercial systems.

This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.

We present Roko, a system that allows parallelization of sequential C codes with a modest user intervention. The user exposes parallelism at the function level by annotating the code with pragmas. Roko defines only two pragmas: the parallel pragma is used to denote function calls that will be executed asynchronously, and the exposed pragma is used to describe data usage of the marked function calls. Architecturally, Roko consists of three components: a compiler that analyzes pragmas, a software environment that spreads the execution over multiple processors, and a hardware support that implements a novel synchronization scheme, versioning. We have designed, implemented and evaluated an FPGA-based prototype of Roko. Our experimental evaluation shows: (i) that few simple pragmas are all that is needed to expose parallelism in benchmark applications and (ii) that Roko can deliver good performance in terms of application speedup.