Detta examensarbete har som syfte att konstruera en prototyp av en testsändare inom Sbandet,2.2 – 2.4 GHz. Arbetet innefattar konstruktion och utveckling av hårdvara och kodför testsändaren, samt tester och optimering av den framtagna prototypen.Koden designades för en FPGA i Quartus II med VHDL. I FPGA:n hanteraskommunikationen mellan användaren och hårdvaran. Designen av mönsterkortet gjordes iprogrammet Altium Designer. Det resulterade i ett kretskort i glasfiber med två lager ochytmonterade komponenter som handlöddes. Huvudkretsarna i hårdvaran är en FPGA, enfrekvensmixer, en lokaloscillator och två olika förstärkare. Lokaloscillatorn genererarbärfrekvensen medans FPGA:n modulerar indata och omvandlar det till datafrekvenser.Mixern blandar bärfrekvensen med data via amplitudmodulering och ger ut en RF-signalsom förstärks innan den sänds ut.Resultatet efter optimering är att testsändaren genererar en ren bärfrekvens inomS-bandet och kompenserar väl för modulationsfel vid generering av RF-signalen. Denöverför data som vid test kan avläsas och valideras av en demoduleringsapparat förflygdata.

Radio Communication technologies are undergoing drastic demand over the past two decades. The precious radio resource, electromagnetic radio spectrum, is in vain as technology advances. It is required to come up with a solution to improve its wise uses. Cognitive Radio enabled by Software-Defined Radio brings an intelligent solution to efficiently use the Radio Spectrum. It is a method to aware the radio communication system to be able to adapt to its radio environment like signal power and free spectrum holes. The approach will pose a question on how to efficiently detect a signal. In this thesis different spectrum sensing algorithm will be explained and a special concentration will be on new sensing algorithm based on the Eigenvalues of received signal. The proposed method adapts blind signal detection approach for applications that lacks knowledge about signal, noise and channel property. There are two methods, one is ratio of the Maximum Eigenvalue to Minimum Eigenvalue and the second is ratio of Signal Power to Minimum Eigenvalue. Random Matrix theory (RMT) is a branch of mathematics and it is capable in analyzing large set of data or in a conclusive approach it provides a correlation points in signals or waveforms. In the context of this thesis, RMT is used to overcome both noise and channel uncertainties that are common in wireless communication. Simulations in MATLAB and real-time measurements in LabVIEW are implemented to test the proposed detection algorithms. The measurements were performed based on received signal from an IF-5641R Transceiver obtained from National Instruments.

This report describes the work of developing a rapid prototyping system for Permanent Magnet Synchronous Motors using LabView FPGA at ABB Corporate Research in Västerås. The aim of the rapid prototyping system is to serve as an additional tool to simulation when evaluating new control algorithms for mechatronic applications. Using LabView FPGA, Field Oriented Control is implemented for a single axis and a multi axis system on the sbRIO 9632 development board from National Instruments. The aim is to develop a controller for multiple axes while optimizing the use of system resources. The report presents the work of testing and evaluating the implementation of the single axis system. The system will be tested in a laboratory test bench to verify its performance. The laboratory results are compared and verified against MATLAB/Simulink simulations of the system. Using the results from the single axis tests as a benchmark the multi axis system is verified and evaluated. The implemented systems proved to provide good regulation of the motor currents for both the single axis and the multi axis system.

The purpose of this study was the hardware implementation of a real time moving object contour extraction.Segmentation of image frames to isolate moving objects followed by contour extraction using digitalmorphology was carried out in this work. Segmentation using temporal difference with median thresholdingapproach was implemented, experimental methods were used to determine the suitable morphological operatorsalong with their structuring elements dimensions to provide the optimum contour extraction.The detector with image resolution of 1280 x1024 pixels and frame rate of 60 Hz was successfully implemented,the results indicate the effect of proper use of morphological operators for post processing and contourextraction on the overall efficiency of the system. An alternative segmentation method based on Stauffer & Grimson algorithm was investigated and proposed which promises better system performance at the expense ofimage resolution and frame rate

A modular and area-efficient 3D graphics accelerator for tile based rendering in FPGA systems has been designed and implemented. The accelerator supports a subset of OpenGL, with features such as mipmapping, multitexturing and blending. The accelerator consists of a software component for projection and clipping of triangles, as well as a hardware component for rasterization, coloring and video output. Trade-offs made between area, performance and functionality have been described and justified. In order to evaluate the functionality and performance of the accelerator, it has been tested with two different applications. / En modulär och utrymmeseffektiv 3D-grafikaccelerator för tile-baserad rendering i FPGA-system har designats och implementerats. Acceleratorn stöder en delmängd av OpenGL med funktioner som mipmapping, multitexturering och blending. Acceleratorn är uppdelad i en mjukvarudel för projektion och klippning av trianglar och en hårdvarudel för rastrering, färgsättning och utritning till skärm. Avvägningar som gjorts mellan area, prestanda och funktionalitet har beskrivits och motiverats. För att evaulera funktionalitet och prestanda har acceleratorn testats med två olika applikationer.

Active safety systems for automobiles in the form of camera systems have evolved rapidly the last ten years, Autoliv Electronics in Linköping develops multiple such systems. In their development process there is a need for a Break out Box (BoB) to record and playback video and CAN data as if the camera system was used in an actual automobile. The aim of this thesis has been to develop a BoB for these camera systems. The work has been divided into three phases; identification of requirements, design of the BoB and implementation of a prototype. The project has addressed four known issues with the currently used BoB; bandwidth, modularity, synchronization and usability. The result is a new BoB which is based on an FPGA connecting to a PC over Gigabit Ethernet. The design is an extendible platform for multiple channels of video, CAN data, other serial data and future extensions. A prototype proves the design concept by successfully recording video for the Autoliv NightVision system onto a PC.

Detta examensarbetet undersöker möjligheten att eliminera de amplitudtoppar som uppstår då flera sinussignaler av slumpmässiga frekvenser adderas. Det som eftersträvas är en signal innehållande flera godtyckliga frekvenser samtidigt som den bibehåller en låg Crestfaktor (eller PAPR). De metoder som tas fram implementeras sedan i en FPGA. Rapporten behandlar de metoder som undersökts både i teoretiska utvärderingar samt i en hårdvaruimplementation. Resultaten visar på att det inte finns någon enkel lösning på problemet, men att en kombination av metoder kan användas för att få en förbättring av signalens Crestfaktor. Metoderna bör balanseras utefter hur mycket av de icke önskvärda amplitudtopparna som ska elimineras, hur snabbt systemet måste vara, hur mycket resurser och hårdvara som finns tillgänglig, samt hur mycket brus som tolereras. De metoder som undersökts grundligast och även implementerats i hårdvara är initial fasfördelning, tid- och frekvensdomänbytesmetod och klippning, vilka tillsammans bildar ett system som genererar en önskvärd signal med låg Crestfaktor. / This thesis investigates the possibility of eliminating the amplitude peaks that arise when several sinusoidal signals of random frequencies are added. The aim is a signal containing several arbitrary frequencies while retaining a low Crest factor (or PAPR). The methods to be developed are then implemented in an FPGA. The report deals with the methods which were examined, both in theoretical evaluations and in a hardware implementation. The results show that there is no easy solution, but that a combination of methods can be used to obtain an improvement of the signal’s Crest factor. These methods should be balanced with respect to how much of the undesirable amplitude is to be eliminated, how fast the system must be, what kind of resources and hardware that is available, and how much noise that can be tolerated. The methods investigated and implemented in hardware are initial phase distribution, time-frequency domain swapping algorithm and clipping, which together form a system that generates a desirable signal with low Crest factor.

The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing. The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible. The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.

Reconfigurable devices are the mainstream in today’s system on chip solutions. Reconfigurable devices have the advantages of reduced cost over their equivalent custom design, quick time to market and the ability to reconfigure the design at will and ease. One such reconfigurable device is an FPGA. In this industrial thesis, the design and implementation of a control process interface using ECP2M FPGA and PCIe communication is accomplished. This control process interface is designed and implemented for a 3-D plotter system called LSC11. In this thesis, the FPGA unit implemented drives the plotter device based on specific timing requirements charted by the customer. The FPGA unit is interfaced to a Host CPU in this thesis (through PCIe communication) for controlling the LSC11 system using a custom software. All the peripherals required for the LSC11 system such as the ADC, DAC, Quadrature decoder and the PWM unit are also implemented as part of this thesis. This thesis also implements an efficient methodology to send all the inputs of the LSC11 system to the Host CPU without the necessity for issuing any cyclic read commands on the Host CPU. The RTL design is synthesised in FPGA and the system is verified for correctness and accuracy. The LSC11 system design consumed 79% of the total FPGA resources and the maximum clock frequency achieved was 130 Mhz. This thesis has been carried out at Abaxor Engineering GmbH, Germany. It is demonstrated in this thesis how FPGA aids in quick designing and implementation of system on chip solutions with PCIe communication.

The initial goal of this report was to implement and compare cosine modulated filter banks. Because of time limitations, focus shifted towards the implementation. Filter banks and multirate systems are important in a vast range of signal processing systems. When implementing a design, there are several considerations to be taken into account. Some examples are word length, number systems and type of components. The filter banks were implemented using a custom made software, especially designed to generate configurable gate level code. The generated code was then synthesized and the results were compared. Some of the results were a bit curious. For example, considerable effort was put into implementing graph multipliers, as these were expected to be smaller and faster than their CSDC (Canonic Signed Digit Code) counterparts. However, with one exception, they turned out to generate larger designs. Another conclusion drawn is that the choice of FPGA is important. There are several things left to investigate, though. For example, a more thorough comparison between CSDC and graph multipliers should be carried out, and other DCT (Discrete Cosine Transform) implementations should be investigated.