Field Programmable Gate Arrays (FPGAs) are widely used in prototyping digital circuits. However commercial FPGAs are not very suitable for asynchronous design. Both the architecture of the FPGAs and the synthesis tools are mostly tailored to synchronous design. Therefore potential advantages of the asynchronous circuits could not be observed when they are implemented on commercial FPGAs. This is shown by designing an asynchronous arithmetic logic unit (ALU), implemented in the style of micropipelines, on the Xilinx Virtex XCV300 FPGA family. The hazard characteristics of the target FPGA have been analyzed and a methodology for selftimed asynchronous circuits has been proposed. The design methodology proposes first designing a hazard-free cell set, and then using relationally placed macros (RPMs) to keep the hazard-free behavior, and incremental design technique to combine modules in upper levels without disturbing their timing characteristics. The performance of the asynchronous ALU has been evaluated in terms of the logic slices occupied in the FPGA and data latencies, and a comparison is made with a synchronous ALU designed on the same FPGA.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

In today&rsquo / s complex technological systems, there is a need of multi tasking several units running in accordance. Each unit is composed of several intelligent microcontroller cards. Each intelligent card performs a different task that the unit is responsible of. For this reason, there is a need of common communication bus between these cards in order to accomplish the task duties. VME (Versa Module Euro-Card) bus is a well known, the most reliable and the commonly used communication bus, even if it was standardized three decades ago. In this thesis work, the world wide accepted VME parallel bus protocol is implemented on FPGA (Field programmable Gate Array). The implementation covers the VME standard slave protocols. The VME Slave Module has been developed by VHDL (Very high level Hardware Description Language). The simulations have been carried over a computer based environment. After the verification of the VHDL code, an Intellectual Property (IP) core is synthesized and loaded into the FPGA. The FPGA based printed circuit board has been designed and the IP core&rsquo / s function has been tested by bus protocol checkers for all of its functionality. The designed hardware has several standard serial communication ports, such as / USB, UART and I2C. Through the developed card and the add-on units, it is also possible to communicate with these serial ports over the VME bus.

In this thesis, we discuss the implementation of a low latency decoding algorithm for turbo codes and repeat accumulate codes and compare the implementation results in terms of maximum available clock speed, resource consumption, error correction performance, and the data (information bit) rate. In order to decrease the latency a parallelized decoder structure is introduced for these mentioned codes and the results are obtained by implementing the decoders on a field programmable gate array. The memory collision problem is avoided by using collision-free interleavers. Through a proposed quantization scheme and normalization approximations, computational issues are handled for overcoming the overflow and underflow issues in a fixed point arithmetic. Also, the effect of different implementation styles are observed.

In this thesis, real time detection of traffic signs using FPGA hardware is presented. Traffic signs have distinctive color and shape properties. Therefore, color and shape based algorithms are chosen to implemented on FPGA. FPGA supports sufficient logic to implement complete systems and sub-systems. Color information of images/frames is used to minimize the search domain of detection process. Using FPGA, real time conversion of YUV space to RGB space is performed. Furthermore, color thresholding algorithm is used to localize the sign in the image/video depending on the color. Edges are the most important image/frame attributes that provide valuable information about the shape of the objects. Sobel edge detection algorithm is implemented on FPGA. After color segmentation, FPGA implementation of Sobel algorithm is used to find the edges of candidate traffic signs in real time. Later, radial symmetry based shape detection algorithm is used to determine circular traffic signs. Each FPGA implemented algorithm is tested by using video sequences and static images. In addition, combined implementation of color based and shape based algorithms are tested. Joint application of color and shape based algorithms are used in order to reduce search domain and the processing time of detection process. Designing architecture on FPGA makes traffic sign detection system portable as a final product and relatively more efficient than the computer based detection systems. The resulting hardware is suitable where cost and compactness constraints are important.

In this thesis, novel implementation methods for FPGA based real-time motion control systems are investigated. These methods are examined for conventional and modern controller topologies as well as peripheral device interfaces which are mutually essential pieces of a motion controller. The developed methods are initially tested one by one to assess the performance of the individual design / and finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC machining center. The developed methods are discussed in terms of their success, resource consumptions and attainable sampling rates.

The present graph cut methods cannot be used directly for real time stereo matching applications because of their recursive structure. Graph cut method is modified to change its recursive structure so that making it suitable for real time FPGA (Field Programmable Gate Array) implementation. The modified method is firstly tested by MATLAB on several data sets, and the results are compared with those of previous studies. Although the disparity results of the modified method are not better than other methods&rsquo / , computation time performance is better. Secondly, the FPGA simulation is performed using real data sets. Finally, the modified method is implemented in FPGA with two PAL cameras at 25 Hz. The computation time of the implementation is 40 ms which is suitable for real time applications.

In this thesis, position and current control systems for a brushless DC (Direct Current) motor are designed and integrated into one FPGA (Field Programmable Gate Array) chip. Experimental results are obtained by driving the brushless DC motors of Control Actuation System of a guided missile. Because of their high performance, brushless DC motors are widely used in Control Actuation Systems of guided missiles. In order to control the motor torque, current controller is designed and implemented in the FPGA. Position controller is designed to fulfill the position commands. A soft processor in the FPGA is used to connect and configure the current controller, position sensor interfaces and communication modules such as UART (Universal Asynchronous Receiver Transmitter) and Spacewire. In addition / position controller is implemented in the soft processor in the FPGA. An FPGA based electronic board is designed and manufactured to implement control algorithms, power converter circuitry and to perform other tasks such as communication with PC (Personal Computer). In order to monitor the behavior of the controllers in real time and to achieve performance tests, a graphical user interface is provided.

The increasing use of the internet demands more powerful routers with higher speed, less power consumption and less physical space occupation. IP lookup operation is one of the major concerns in today&rsquo / s routers for providing such attributes. To accomplish IP lookup on routers, hardware or software based solutions can be used. In this thesis, an SRAM based pipelined architecture proposed earlier for ASIC implementation is re-designed and implemented on an FPGA in the form of a BRAM based pipelined 8x8 torus architecture using Xilinx ISE and simulated and verified using Modelsim Simulator. Some necessary modifications and improvements for FPGA implementation are carried out. The results of our experiments, which are performed for a real router lookup table and a real time traffic load with various optimizations, are also presented. Our study and design effort demonstrates the feasibility of the FPGA implementation of the proposed technique, of course with a considerable performance penalty.

¡@¡@The first topic of this thesis is a high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage when the design is implemented by TSMC (Taiwan Semiconductor Manufacturing Company) 0.35um CMOS 1P4M technol- ogy. ¡@¡@The second topic of this thesis is an 1-to-4 joystick enhanced interface which can be attached to SONY PS2 (playstation 2) is developed. The enhanced interface can allow 4 persons to play simultaneously through one port at the original game console. A total of 8 players can be supported when two of the interfaces hook up with both joystick ports of the console. The multiple player entertainment effect can be drastically enhanced by the usage of such an interface.