This thesis presents an energy monitoring system to measure energy consumption of software applications to support security and power management for embedded devices. The proposed system is composed of an Actel Fusion device and a custom designed energy measurement circuit. The Fusion device measures the voltage and the current of the target device at a defined sampling rate. The energy measurement circuit is designed as a current integrator over fixed intervals using the switched-capacitor integrator technique to store energy information of the target device within Fusion’s sampling intervals. This circuit is designed to accommodate the low sampling rate of the Fusion device. Experimental results showed that the Fusion device allows the measurement of the energy of the target device at a minimum rate of 15 µs. The energy measurement circuit is implemented using the 65 nm CMOS technology. Simulation results showed that this circuit provides 91%~97% average energy measurement accuracy.

The Iterative Closest Point (ICP) algorithm is one of the most commonly used range image processing methods. However, slow operational speeds and high input band-widths limit the use of ICP in high-speed real-time applications. This thesis presents and examines a novel hardware implementation of a high-speed ICP object tracking system that uses stereo vision disparities as input. Although software ICP trackers already exist, this innovative hardware tracker utilizes the efficiencies of custom hardware processing, thus enabling faster high-speed real-time tracking. A custom hardware design has been implemented in an FPGA to handle the inherent bottlenecks that result from the large input and processing band-widths of the range data. The hardware ICP design consists of four stages: Pre-filter, Transform, Nearest Neighbor, and Transform Recovery. This custom hardware has been implemented and tested on various objects, using both software simulation and hardware tests. Results indicate that the tracker is able to successfully track free-form objects at over 200 frames-per-second along arbitrary paths. Tracking errors are low, in spite of substantial noisy stereo input. The tracker is able to track stationary paths within 0.42mm and 1.42degs, linear paths within 1.57mm and 2.80degs, and rotational paths within 0.39degs axis error. With further degraded data by occlusion, the tracker is able to handle 60% occlusion before a slow decline in performance. The high-speed hardware implementation (that uses 16 parallel nearest neighbor circuits), is more then five times faster than the software K-D tree implementation. This tracker has been designed as the hardware component of ‘FastTrack’, a high frame rate, stereo vision tracking system, that will provide a known object’s pose in real-time at 200 frames per second. This hardware ICP tracker is compact, lightweight, has low power requirements, and is integratable with the stereo sensor and stereo extraction components of the FastTrack’ system on a single FPGA platform. High-speed object tracking is useful for many innovative applications, including advanced spaced-based robotics. Because of this project’s success, the ‘FastTrack’ system will be able to aid in performing in-orbit, automated, remote satellite recovery for maintenance. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-07-15 22:50:30.369

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The revolutionary advancements in the field of bioinformatics have opened new horizons in biological and pharmaceutical research. However, the existing bioinformatics tools are unable to meet the computational demands, due to the recent exponential growth in biological data. So there is a dire need to build future bioinformatics platforms incorporating modern parallel computation techniques. In this work, we investigate FPGA based acceleration of these applications, using High-Level Synthesis. High-Level Synthesis tools enable automatic translation of abstract specifications to the hardware design, considerably reducing the design efforts. However, the generation of an efficient hardware using these tools is often a challenge for the designers. Our research effort encompasses an exploration of the techniques and practices, that can lead to the generation of an efficient design from these high-level synthesis tools. We illustrate our methodology by accelerating a widely used application -- HMMER -- in bioinformatics community. HMMER is well-known for its compute-intensive kernels and data dependencies that lead to a sequential execution. We propose an original parallelization scheme based on rewriting of its mathematical formulation, followed by an in-depth exploration of hardware mapping techniques of these kernels, and finally show on-board acceleration results. Our research work demonstrates designing flexible hardware accelerators for bioinformatics applications, using design methodologies which are more efficient than the traditional ones, and where resulting designs are scalable enough to meet the future requirements.

Soft processing engines make FPGA programming simpler for software programmers. TILT is a multithreaded soft processing engine that contains multiple deeply pipelined and varying latency functional units. In this thesis, we present a compiler framework for compiling and scheduling for TILT. By using the compiler to generate schedules and manage hardware we create computationally dense designs (high throughput per hardware area) which make compelling processing engines. High schedule density is achieved by mixing instructions from different threads and by prioritizing the longest path of data flow graphs. Averaged across benchmark kernels we can achieve 90% of the theoretical throughput, and can reduce the performance gap relative to custom hardware from 543x for a scalar processor to only 4.41x by replicating TILT cores up to a comparable area cost. We also present methods of quickly navigating the design space and predicting the area of hardware configurations.

Soft processing engines make FPGA programming simpler for software programmers. TILT is a multithreaded soft processing engine that contains multiple deeply pipelined and varying latency functional units. In this thesis, we present a compiler framework for compiling and scheduling for TILT. By using the compiler to generate schedules and manage hardware we create computationally dense designs (high throughput per hardware area) which make compelling processing engines. High schedule density is achieved by mixing instructions from different threads and by prioritizing the longest path of data flow graphs. Averaged across benchmark kernels we can achieve 90% of the theoretical throughput, and can reduce the performance gap relative to custom hardware from 543x for a scalar processor to only 4.41x by replicating TILT cores up to a comparable area cost. We also present methods of quickly navigating the design space and predicting the area of hardware configurations.

Traditionally large format displays have been achieved using software. A new technique of using hardware based anywhere pixel routing is explored in this thesis. Information stored in a Look Up Table (LUT) in the hardware can be used to tile two image streams to produce a seamless image display. This thesis develops a 1 input-image 1 output-image system that implements arbitrary image warping on the image, based a LUT stored in memory. The developed system control mechanism is first validated using simulation results. It is next validated via implementation to a Field Programmable Gate Array (FPGA) based hardware prototype and appropriate experimental testing. It was validated by changing the contents of the LUT and observing that the resulting changes on the pixel mapping were always correct.

Percent Moisture Content (MC %) of wood is defined to be the weight of the moisture in the wood divided by the weight of the dry wood times 100%. Equilibrium Moisture Content (EMC), moisture content at environmental equilibrium is a very important metric affecting the performance of wood in many applications. For best performance in many applications, the goal is to maintain this value between 6% and 8%. EMC value is a function of the temperature and the relative humidity of the surrounding air of wood. It is very important to maintain this value while processing, storing or finishing the wood. This thesis develops a special purpose sensor and processor system to be implemented as a small hand-held device used to sense, calculate and display the value of EMC of wood depending on surrounding environmental conditions. Wood processing industry personnel would use the hand-held EMC calculating and display device to prevent many potential problems that can show significant affect on the performance of wood. The design of the EMC device requires the use of sensors to obtain the required inputs of temperature and relative humidity. In this thesis various market available sensors are compared and appropriate sensor is chosen for the design. The calculation of EMC requires many arithmetic operations with stringent precision requirements. Various arithmetic algorithms and systems are compared in terms of meeting required arithmetic functionality, precision requirements, and silicon implementation area and gate count, and a suitable choice is made. The resulting processor organization and design is coded in VHDL using the Xilinx ISE 6.2.03i tool set. The design is synthesized, validated via VHDL virtual prototype simulation, and implemented to a Xilinx Spartan2E FPGA for experimental hardware prototype testing and evaluation. It is tested over various ranges of temperature and relative humidity. Comparison of experimentally calculated EMC values with the theoretical values of EMC derived for corresponding temperature and relative humidity points resulted in validation of the EMC processor architecture, functional performance and arithmetic precision requirements.

Fault detection and location algorithms have allowed for the power industry to alter the power grid from the traditional model to becoming a smart grid. This thesis implements an already established algorithm for detecting faults, as well as an impedance-based algorithm for detecting where on the line the fault has occurred and develops a smart algorithm for future HDL conversion using Simulink. Using the algorithms, the ways in which this implementation can be used to create a smarter grid are the fundamental basis for this research. Simulink was used to create a two-bus power system, create environment variables, and then Matlab was used to program the algorithm such that it could be FPGA-implementable, where the ways in which one can retrieve the data from a power line has been theorized. This novel approach to creating a smarter grid was theorized and created such that real-world applications may be further implemented in the future.

Au cours des dix dernières années, les capacités technologiques de transmission vidéo rendent possible une panoplie d'applications de télésanté. Ce média permet en effet la participation de médecins spécialisés à des interventions médicales ayant lieu à des endroits distants. Cependant, lorsque ces dernières se déroulent loin des grands centres, les infrastructures de télécommunication n'offrnt pas un débit assez important pour permettre à la fois une transmission d'images fluides et de bonne qualité. Un des moyens entrepris pour pallier ce problème est l'utilisation d'encodeur et décodeur vidéo (CODEC) permettant de compresser les images avant leur transmission et de les décompresser à la réception. Il existe un bon nombre de CODEC vidéo offrant différent compromis entre la qualité d'image, la rapidité de compression, la latence initiale de traitement et la robustesse du protocole de transmission. Malheureusement, aucun n'est en mesure de rencontrer simultanément toutes les exigences définies en télésanté. Un des problèmes majeurs réside dans le délai de traitement initial causé par la compression avec perte du CODEC. L'objet de la recherche s'intéresse donc à deux CODEC qui répondent aux exigences de délais de traitement et de qualité d'image en télésanté, et plus particulièrement pour une application de téléassistance en salle d'urgence. L'emphase est mise sur les modules de quantification des CODEC qui utilisent la transformée en cosinus discrète. Cette transformée limite la transmission des images vidéo fluide et quasi sans délais en raison des délais de traitement initiaux issus des nombreuses manipulations arithmétiques qu'elle requiert. À l'issu de la recherche, une structure efficace de la transformée en cosinus est proposée afin de présenter une solution au temps de latence des CODEC et ainsi de répondre aux exigences de télécommunication en télésanté. Cette solution est implémentée dans un CODEC JPEG développé en VHDL afin de simuler un contexte d'application réelle.